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<p>Universal cryogenic computing, encompassing von Neumann, neuromorphic and quantum computing, paves the way for future big-data processing with high energy efficiency. Complementary metal oxide semiconductor (CMOS) technology operating at cryogenic temperatures with ultra-low power consumption is a key component of this advancement. However, classical CMOS technology, designed for room temperature applications, suffers from band-tail effects at cryogenic levels, leading to an increased subthreshold swing and decreased mobility values. In addition, threshold voltages are enlarged. Thus, classical CMOS technology fails to meet the low power requirements when cooled close to zero Kelvin. In this Perspective, we show that steep slope cryogenic devices can be realized by screening the band tails with the use of high-<i>k</i> dielectrics and wrap-gate architectures and/or reducing them through the optimization of the surfaces and interfaces within the transistors. Cryogenic device functionality also strongly benefits from appropriate source/drain engineering employing dopant segregation from silicides. Furthermore, the threshold voltage control can be realized with back-gating, work-function engineering and dipole formation. As a major implication, future research and development towards cryogenic CMOS technology requires a combination of these approaches to enable universal cryogenic computing at the necessary ultra-low power levels.</p>

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Ultra-low-power cryogenic complementary metal oxide semiconductor technology

  • 期刊论文

  • 发表日期：

    2025年4月1日

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  • Qing-Tai Zhao,
  • Yi Han,
  • Hung-Chi Han,
  • Lars R. Schreiber,
  • Tsung-En Lee,
  • Hung-Li Chiang,
  • Iuliana Radu,
  • Christian Enz,
  • Detlev Grützmacher,
  • Christoph Stampfer,
  • Shinichi Takagi,
  • Joachim Knoch

摘要

Universal cryogenic computing, encompassing von Neumann, neuromorphic and quantum computing, paves the way for future big-data processing with high energy efficiency. Complementary metal oxide semiconductor (CMOS) technology operating at cryogenic temperatures with ultra-low power consumption is a key component of this advancement. However, classical CMOS technology, designed for room temperature applications, suffers from band-tail effects at cryogenic levels, leading to an increased subthreshold swing and decreased mobility values. In addition, threshold voltages are enlarged. Thus, classical CMOS technology fails to meet the low power requirements when cooled close to zero Kelvin. In this Perspective, we show that steep slope cryogenic devices can be realized by screening the band tails with the use of high-k dielectrics and wrap-gate architectures and/or reducing them through the optimization of the surfaces and interfaces within the transistors. Cryogenic device functionality also strongly benefits from appropriate source/drain engineering employing dopant segregation from silicides. Furthermore, the threshold voltage control can be realized with back-gating, work-function engineering and dipole formation. As a major implication, future research and development towards cryogenic CMOS technology requires a combination of these approaches to enable universal cryogenic computing at the necessary ultra-low power levels.