<p>Devices based on two-dimensional materials, such as molybdenum disulfide (MoS₂), could be used to build neuromorphic compute-in-memory hardware due to their high electrostatic controllability. Scaling up such hardware is key to enhancing its application in edge artificial intelligence platforms. However, development has been limited due to a trade-off between weight precision and energy efficiency: methods to increase weight precision (such as using elevated operating voltages to encode other conductance states or using calibration and compensation schemes to mitigate device-to-device variations) are effective at improving performance but are energy intensive. Here we report on an in-hardware signal-folding scheme that can provide both high weight precision and high energy efficiency. The approach uses two folding schemes—input signal folding and weight conductance folding—to predefine signals applied for vector–matrix multiplication, and we implement the schemes using a vertical one-transistor–one-resistor MoS₂ crossbar array. In both schemes, the signals are encoded into two combinatorial folded signals. The input signal folding decreases the operating voltage, whereas the weight conductance folding circumvents device-to-device variations to expand weight precision. Compared with computing with the unfolded signal, our method can reduce the power consumption of vector–matrix multiplication by up to 90%, while achieving similar accuracy and without calibration or compensation schemes.</p>