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<p>Non-volatile compute-in-memory macros can reduce data transfer between processing and memory units, providing fast and energy-efficient artificial intelligence computations. However, the non-volatile compute-in-memory architecture typically relies on analogue computing, which is limited in terms of accuracy, scalability and robustness. Here we report a 64-kb non-volatile digital compute-in-memory macro based on 40-nm spin-transfer torque magnetic random-access memory technology. Our macro features in situ multiplication and digitization at the bitcell level, precision-reconfigurable digital addition and accumulation at the macro level and a toggle-rate-aware training scheme at the algorithm level. The macro supports lossless matrix–vector multiplications with flexible input and weight precisions (4, 8, 12 and 16 bits), and can achieve a software-equivalent inference accuracy for a residual network at 8-bit precision and physics-informed neural networks at 16-bit precision. Our non-volatile compute-in-memory macro has computation latencies of 7.4–29.6 ns and energy efficiencies of 7.02–112.3 tera-operations per second per watt for fully parallel matrix–vector multiplications across precision configurations ranging from 4 to 16 bits.</p>

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A lossless and fully parallel spintronic compute-in-memory macro for artificial intelligence chips

  • 期刊论文

  • 发表日期：

    2025年10月16日

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  • Humiao Li,
  • Zheng Chai,
  • Weirong Dong,
  • Junjie He,
  • Ruijie Peng,
  • Shiheng Li,
  • Zhen Kong,
  • Xihui Yuan,
  • Xianwang Wang,
  • Zhengke Yang,
  • Haoran Lyu,
  • Haofeng Yu,
  • Xue Zhou,
  • Jiamin Li,
  • Feichi Zhou,
  • Yida Li,
  • Zongben Xu,
  • Tai Min,
  • Longyang Lin

摘要

Non-volatile compute-in-memory macros can reduce data transfer between processing and memory units, providing fast and energy-efficient artificial intelligence computations. However, the non-volatile compute-in-memory architecture typically relies on analogue computing, which is limited in terms of accuracy, scalability and robustness. Here we report a 64-kb non-volatile digital compute-in-memory macro based on 40-nm spin-transfer torque magnetic random-access memory technology. Our macro features in situ multiplication and digitization at the bitcell level, precision-reconfigurable digital addition and accumulation at the macro level and a toggle-rate-aware training scheme at the algorithm level. The macro supports lossless matrix–vector multiplications with flexible input and weight precisions (4, 8, 12 and 16 bits), and can achieve a software-equivalent inference accuracy for a residual network at 8-bit precision and physics-informed neural networks at 16-bit precision. Our non-volatile compute-in-memory macro has computation latencies of 7.4–29.6 ns and energy efficiencies of 7.02–112.3 tera-operations per second per watt for fully parallel matrix–vector multiplications across precision configurations ranging from 4 to 16 bits.