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<p>This work presents simulation results on a silicon-compatible electrostatically induced electron–hole bilayer (EHB) in a multi-bridge channel FET (MBCFET) enabled through middle-gate work-function engineering and vertical bias coordination. In this work, the term EHB refers to the electrostatically induced spatial separation of electron-rich and hole-rich regions within the silicon channel. Unlike conventional excitonic electron–hole bilayer systems, the proposed architecture does not rely on strong interlayer Coulomb coupling or many-body quantum effects. Instead, the bilayer configuration is established through gate work-function engineering and electrostatic bias control. Sentaurus TCAD results show a substantial improvement in drain current, reduced Drain-Induced Barrier Lowering (DIBL), and enhanced transconductance compared to a conventional double-gate MOSFET (DG MOSFET) of the same geometry. The architecture is predicted to achieve strong suppression of peak electric field at the source corner, contributing to improved electrostatic integrity and lower leakage. Compared with the conventional MBCFET, the proposed EHB-MBCFET achieves nearly 27% higher ON-state current under the investigated operating conditions. The device also demonstrates improved electrostatic control, reduced DIBL, a low OFF-state current, and a minimum Subthreshold Slope (SS) of approximately 67 mV/dec under optimized bias conditions. When employed in SRAM, the proposed EHB-MBCFET enhances the hold static noise margin by about 31.5%–100.9% compared with previously reported designs, while maintaining competitive write performance and up to <InlineEquation ID="IEq1"><EquationSource Format="TEX">\(\sim\)</EquationSource></InlineEquation>85% improvement in read noise margin. Owing to its purely electrostatic formation and CMOS-compatible material stack, the proposed EHB-MBCFET offers a promising pathway for compact, low-power and high-performance nanoscale device design.</p>

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Electrostatically induced electron hole carrier separation in a silicon multi bridge channel FET for enhanced SRAM performance

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  • 出版模式：

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  • 发表日期：

    2026年7月29日

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  • S. Ashok Kumar,
  • Binola K. Jebalin I.V,
  • Husna Hamza,
  • Julie Roslita Rusli,
  • Nirmal D

摘要

This work presents simulation results on a silicon-compatible electrostatically induced electron–hole bilayer (EHB) in a multi-bridge channel FET (MBCFET) enabled through middle-gate work-function engineering and vertical bias coordination. In this work, the term EHB refers to the electrostatically induced spatial separation of electron-rich and hole-rich regions within the silicon channel. Unlike conventional excitonic electron–hole bilayer systems, the proposed architecture does not rely on strong interlayer Coulomb coupling or many-body quantum effects. Instead, the bilayer configuration is established through gate work-function engineering and electrostatic bias control. Sentaurus TCAD results show a substantial improvement in drain current, reduced Drain-Induced Barrier Lowering (DIBL), and enhanced transconductance compared to a conventional double-gate MOSFET (DG MOSFET) of the same geometry. The architecture is predicted to achieve strong suppression of peak electric field at the source corner, contributing to improved electrostatic integrity and lower leakage. Compared with the conventional MBCFET, the proposed EHB-MBCFET achieves nearly 27% higher ON-state current under the investigated operating conditions. The device also demonstrates improved electrostatic control, reduced DIBL, a low OFF-state current, and a minimum Subthreshold Slope (SS) of approximately 67 mV/dec under optimized bias conditions. When employed in SRAM, the proposed EHB-MBCFET enhances the hold static noise margin by about 31.5%–100.9% compared with previously reported designs, while maintaining competitive write performance and up to \(\sim\)85% improvement in read noise margin. Owing to its purely electrostatic formation and CMOS-compatible material stack, the proposed EHB-MBCFET offers a promising pathway for compact, low-power and high-performance nanoscale device design.