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<p>To reliably capture quantum and scattering phenomenon, it has been a common practice to design the ultra-scaled gate-all-around transistors (GAAFET) by solving the subband Boltzmann transport equation (BTE), e.g., in synopsys sentaurus QTX (S-QTX). However, it is extremely computationally intensive to solve the subband-BTE using conventional numerical methods. For instance, it may take several hours, or even days, to obtain one current-voltage (IV) curve, hindering efficient design and development of sub-10&#xa0;nm devices. To mitigate this problem, here we propose a fast subband-BTE solver using the Fourier neural operator (FNO), which can significantly accelerate the convergence speed and can achieve acceleration by more than one order of magnitude without sacrificing accuracy, compared to state-of-the-art numerical methods as implemented in the mainstream S-QTX. The proposed method might be useful to shorten turnaround time during design-technology co-optimization (DTCO) of sub-10&#xa0;nm advanced technology nodes.</p>

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A fourier neural operator-based subband-BTE solver for sub-10 nm ultra-scaled devices

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年7月24日

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  • Zhehan Pang,
  • Hao Ruan,
  • Youyuan Tao,
  • Xi Ding,
  • Hao Zhang,
  • Fei Liu,
  • Han Wang,
  • Jie Liu

摘要

To reliably capture quantum and scattering phenomenon, it has been a common practice to design the ultra-scaled gate-all-around transistors (GAAFET) by solving the subband Boltzmann transport equation (BTE), e.g., in synopsys sentaurus QTX (S-QTX). However, it is extremely computationally intensive to solve the subband-BTE using conventional numerical methods. For instance, it may take several hours, or even days, to obtain one current-voltage (IV) curve, hindering efficient design and development of sub-10 nm devices. To mitigate this problem, here we propose a fast subband-BTE solver using the Fourier neural operator (FNO), which can significantly accelerate the convergence speed and can achieve acceleration by more than one order of magnitude without sacrificing accuracy, compared to state-of-the-art numerical methods as implemented in the mainstream S-QTX. The proposed method might be useful to shorten turnaround time during design-technology co-optimization (DTCO) of sub-10 nm advanced technology nodes.