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<p>Large-area active-matrix panels suffer from timing distortion caused by resistive–capacitive (RC) accumulation along extended signal lines. To minimize signal propagation length and reduce accumulated RC loading, a distributed gate-driving architecture is proposed. The design embeds multiple gate driver units within a region-segmented pixel array, utilizing a clustered and shielded layout to suppress parasitic coupling. Simulations for a 27-inch AMOLED panel demonstrated a 57% reduction in signal delay, consistent with the Elmore delay approximation. The gate signal delay variation across the panel, which was approximately 4.0 µs in the conventional gate driver, became negligible with the proposed architecture, ensuring sufficient threshold voltage compensation time. A prototype fabricated using low-temperature polycrystalline silicon thin-film transistors exhibited uniform signal timing, 91.4% luminance uniformity, and a black luminance of 0.009&#xa0;cd/m<sup>2</sup>. These results validate that the proposed gate driver architecture ensures stable signal delivery, substantially reduces timing non-uniformity, and enhances overall electro-optical performance for large, high-resolution display systems.</p>

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Region-segmented gate driver for mitigating RC delay in large-area automotive OLED displays

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年4月9日

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  • Dahye Shim,
  • Seok Gyu Hong,
  • Yong-Min Jeong,
  • Eui-Hyun Chung,
  • Chul Nam,
  • Sanghoon Jung,
  • Joonyoung Yang,
  • Hyun Jae Kim

摘要

Large-area active-matrix panels suffer from timing distortion caused by resistive–capacitive (RC) accumulation along extended signal lines. To minimize signal propagation length and reduce accumulated RC loading, a distributed gate-driving architecture is proposed. The design embeds multiple gate driver units within a region-segmented pixel array, utilizing a clustered and shielded layout to suppress parasitic coupling. Simulations for a 27-inch AMOLED panel demonstrated a 57% reduction in signal delay, consistent with the Elmore delay approximation. The gate signal delay variation across the panel, which was approximately 4.0 µs in the conventional gate driver, became negligible with the proposed architecture, ensuring sufficient threshold voltage compensation time. A prototype fabricated using low-temperature polycrystalline silicon thin-film transistors exhibited uniform signal timing, 91.4% luminance uniformity, and a black luminance of 0.009 cd/m2. These results validate that the proposed gate driver architecture ensures stable signal delivery, substantially reduces timing non-uniformity, and enhances overall electro-optical performance for large, high-resolution display systems.