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<p>The Versatile Video Coding (VVC) standard is aimed to achieve higher compression efficiency compared with HEVC (H.265) at the cost of coding complexity. Many advanced tools are used to achieve this, and Multiple Transform Selection (MTS) is one such tool, which adds the coding complexity. In real time the support of different multiple transforms like DCT-II, DCT-VIII, and DST-VII with varying multiple block sizes significantly increases the power consumption and hardware complexity. This proposed work presents a power-efficient 2-D transform architecture that integrates an adaptable 1-D transform design with a Unified Hybrid Transpose Memory (UHTM). Customized low-power techniques are incorporated to minimize dynamic switching activity while maintaining the high throughput of 4k@30fps. According to the obtained results after implementation, the proposed design consumes dynamic power of 129mW which shows a substantial power saving compared to latest works, without compromising the overall performance, scalability and efficiency. The architecture is highly suitable for real-time ultra-HD video processing in video coding applications.</p>

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Power-efficient hardware architecture for 2-D multiple transforms in VVC

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年2月19日

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  • Murali Babu Palagani,
  • Purnachand Nalluri

摘要

The Versatile Video Coding (VVC) standard is aimed to achieve higher compression efficiency compared with HEVC (H.265) at the cost of coding complexity. Many advanced tools are used to achieve this, and Multiple Transform Selection (MTS) is one such tool, which adds the coding complexity. In real time the support of different multiple transforms like DCT-II, DCT-VIII, and DST-VII with varying multiple block sizes significantly increases the power consumption and hardware complexity. This proposed work presents a power-efficient 2-D transform architecture that integrates an adaptable 1-D transform design with a Unified Hybrid Transpose Memory (UHTM). Customized low-power techniques are incorporated to minimize dynamic switching activity while maintaining the high throughput of 4k@30fps. According to the obtained results after implementation, the proposed design consumes dynamic power of 129mW which shows a substantial power saving compared to latest works, without compromising the overall performance, scalability and efficiency. The architecture is highly suitable for real-time ultra-HD video processing in video coding applications.