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<p>This study presents a layer-wise, verification-oriented methodology for transferring computational models developed in MATLAB to Field-Programmable Gate Array (FPGA)–based hardware accelerators while preserving functional equivalence in a quantitatively verifiable manner. Existing MATLAB-to-FPGA conversion tools primarily focus on synthesis and resource optimization. In contrast, the proposed approach introduces a validated workflow that explicitly ensures layer-wise numerical consistency between software and hardware implementations. At each stage of the MATLAB–C++–FPGA workflow, golden output based verification is performed by comparing layer activations from a high-level synthesis (HLS)–based C + + model and the hardware implementation against reference outputs obtained in MATLAB. Layer-level accuracy is evaluated using the mean absolute error (MAE) metric, with all layers achieving MAE values below 1.5 × 10⁻³ when comparing MATLAB floating-point (FP) reference outputs with the HLS-based C + + model. Hardware validation is conducted on the Python Productivity for Zynq (PYNQ)-Z1 FPGA board. The convolutional layers are executed on the programmable logic (PL) using fixed-point arithmetic, while softmax and verification computations are performed on the processing system (PS) using FP arithmetic. This design maintains an end-to-end data flow from FP to fixed-point on the PL and back to FP, ensuring numerical accuracy and traceability across computational domains. The results demonstrate that the proposed method provides a reproducible verification framework for one-dimensional (1D) convolutional neural network (CNN)–based models and complements performance-oriented FPGA acceleration workflows by introducing a quantitatively traceable accuracy-preservation mechanism.</p>

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Towards the transformation of MATLAB models into FPGA-Based hardware accelerators

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年1月11日

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  • Sezen Bal

摘要

This study presents a layer-wise, verification-oriented methodology for transferring computational models developed in MATLAB to Field-Programmable Gate Array (FPGA)–based hardware accelerators while preserving functional equivalence in a quantitatively verifiable manner. Existing MATLAB-to-FPGA conversion tools primarily focus on synthesis and resource optimization. In contrast, the proposed approach introduces a validated workflow that explicitly ensures layer-wise numerical consistency between software and hardware implementations. At each stage of the MATLAB–C++–FPGA workflow, golden output based verification is performed by comparing layer activations from a high-level synthesis (HLS)–based C + + model and the hardware implementation against reference outputs obtained in MATLAB. Layer-level accuracy is evaluated using the mean absolute error (MAE) metric, with all layers achieving MAE values below 1.5 × 10⁻³ when comparing MATLAB floating-point (FP) reference outputs with the HLS-based C + + model. Hardware validation is conducted on the Python Productivity for Zynq (PYNQ)-Z1 FPGA board. The convolutional layers are executed on the programmable logic (PL) using fixed-point arithmetic, while softmax and verification computations are performed on the processing system (PS) using FP arithmetic. This design maintains an end-to-end data flow from FP to fixed-point on the PL and back to FP, ensuring numerical accuracy and traceability across computational domains. The results demonstrate that the proposed method provides a reproducible verification framework for one-dimensional (1D) convolutional neural network (CNN)–based models and complements performance-oriented FPGA acceleration workflows by introducing a quantitatively traceable accuracy-preservation mechanism.