Scholarlink

<p>Reversible logic is a design paradigm suitable to energy-efficient digital systems and has lately received recognition as a viable option for designing sophisticated digital applications. It possesses the capacity to revolutionize progress in quantum and low-power computing. This research presents an innovative reversible gate designed with merely 10 transistors. The suggested gate includes capabilities for several logic operations such as XOR, XNOR, NOT, NAND, NOR, half-adder and parity generator. This proposed design can attain a minimal quantum cost, which is strongly advocated in quantum computing. We have verified the design’s resilience using Monte Carlo and process corner analysis after modeling it with Cadence Virtuoso at 45 nm technology and 1 V supply voltage. This confirms the robustness of the design amidst variation. In contrast to current reversible gates, the proposed structure achieves an 18 percent reduction in delay and a 12 percent reduction in power delay product, rendering it an appealing option for high-speed and low-energy circuit design. To illustrate its adaptability in alternative designs, we have utilized it to the construction of a 4-bit binary-to-Gray code converter circuit.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Robust and compact reversible logic gate for low-power and high-performance computing

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2025年12月4日

查看全文
  • Anju Rajput,
  • Renu Kumawat,
  • Avireni Srinivasulu,
  • Jyoti Sharma

摘要

Reversible logic is a design paradigm suitable to energy-efficient digital systems and has lately received recognition as a viable option for designing sophisticated digital applications. It possesses the capacity to revolutionize progress in quantum and low-power computing. This research presents an innovative reversible gate designed with merely 10 transistors. The suggested gate includes capabilities for several logic operations such as XOR, XNOR, NOT, NAND, NOR, half-adder and parity generator. This proposed design can attain a minimal quantum cost, which is strongly advocated in quantum computing. We have verified the design’s resilience using Monte Carlo and process corner analysis after modeling it with Cadence Virtuoso at 45 nm technology and 1 V supply voltage. This confirms the robustness of the design amidst variation. In contrast to current reversible gates, the proposed structure achieves an 18 percent reduction in delay and a 12 percent reduction in power delay product, rendering it an appealing option for high-speed and low-energy circuit design. To illustrate its adaptability in alternative designs, we have utilized it to the construction of a 4-bit binary-to-Gray code converter circuit.