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<p>Modern multimedia systems demand high-speed and low-power arithmetic units, especially in image processing applications where full accuracy is often unnecessary. Traditional exact multipliers, while precise, impose substantial overhead in terms of power, delay, and hardware complexity. Approximate computing has emerged as a promising paradigm to relax accuracy constraints in favor of performance gains. However, designing efficient approximate compressors that offer both minimal error and hardware efficiency remains a challenge. In this study, we propose novel 4:2 and 7:2 approximate compressor architectures based on current-mode logic and pass-transistor techniques, optimized for CNTFET 32&#xa0;nm technology. These compressors are integrated into two- and three-stage Dadda multipliers for 8 × 8 and 16 × 16 image processing tasks. Simulation results demonstrate significant reductions in power-delay product and transistor count, while maintaining competitive image quality based on PSNR and MSSIM metrics. The proposed designs provide a balanced trade-off between computational efficiency and perceptual accuracy, making them ideal for energy-constrained multimedia systems.</p>

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Energy efficient approximate compressor architectures for high performance image multiplication in CNTFET technology

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年10月16日

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  • Pegah Foroutan,
  • Keivan Navi

摘要

Modern multimedia systems demand high-speed and low-power arithmetic units, especially in image processing applications where full accuracy is often unnecessary. Traditional exact multipliers, while precise, impose substantial overhead in terms of power, delay, and hardware complexity. Approximate computing has emerged as a promising paradigm to relax accuracy constraints in favor of performance gains. However, designing efficient approximate compressors that offer both minimal error and hardware efficiency remains a challenge. In this study, we propose novel 4:2 and 7:2 approximate compressor architectures based on current-mode logic and pass-transistor techniques, optimized for CNTFET 32 nm technology. These compressors are integrated into two- and three-stage Dadda multipliers for 8 × 8 and 16 × 16 image processing tasks. Simulation results demonstrate significant reductions in power-delay product and transistor count, while maintaining competitive image quality based on PSNR and MSSIM metrics. The proposed designs provide a balanced trade-off between computational efficiency and perceptual accuracy, making them ideal for energy-constrained multimedia systems.