This article presents an optimized low-power, energy-efficient, high-resolution Sigma-Delta Analog-to-Digital Converter ( \(\Sigma\) - \(\Delta\) ADC) for biomedical IoT (Internet of Things) applications. Advances in technology demand IoT devices to process huge data with high precision and lower power dissipation. This increases the expectations from data converters used in these portable devices. The \(\Sigma\) - \(\Delta\) ADC proposed in this work is designed and analyzed using a 180 nm SCL CMOS technology node in the Cadence Virtuoso environment. \(\Sigma\) - \(\Delta\) modulator uses a folded-cascode and a two-stage amplifier to achieve an optimal balance between power consumption and accuracy. The folded-cascode amplifier exhibits a gain of 76 dB, a phase margin of \(56^\circ\) , and a power consumption of 250 \(\upmu \hbox {W}\) . In comparison, the two-stage amplifier produces a gain of 80.5 dB, a phase margin of \(64^\circ\) , and a significantly lower power dissipation of 72 \(\upmu \hbox {W}\) . To further reduce power, a dynamic comparator circuit is employed in the binary quantizer to replace the two-stage amplifier. The modulator samples at a clock frequency of 1.28 MHz and converts the analog signal into high-frequency digital bit streams. The digital filter and decimation block are designed together. A second-order Cascoded Integrator Comb (CIC) filter is designed. The designed filter replaces the traditional integrator with a counter to optimize power consumption. The filter decimates the high-frequency pulse code modulated bit stream into a 14-bit resolution digital signal. This article also presents in-depth the transistor-level designs of all components used, along with certain important aspects of the design procedure. The post layout results demonstrate that the \(\Sigma\) - \(\Delta\) converter attains an Effective Number of Bits (ENOB) of 13.995, a Signal-to-Noise Ratio (SNR) of 84.8 dB, and a Figure of Merit (FOM) of 20.41 fJ/conversion. With an oversampling ratio (OSR) of 128, the ADC operates efficiently, consuming only 0.498 mW of power. The layout area of the proposed ADC is \(0.0896~\text {mm}^2\) . The proposed ADC design meets the performance requirements of biomedical IoT devices.
