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<p>In order to improve the performances of 4 two-input NAND so that it can be better used in the aerospace application field and in harsh environments, 4 two-input NAND gate chips were designed and successfully fabricated in this paper, based on 1.2 <InlineEquation ID="IEq1"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="41598_2025_14874_Article_IEq1.gif" Format="GIF" Height="13" Rendition="HTML" Resolution="72" Type="Linedraw" Width="12" /> </InlineMediaObject> <EquationSource Format="TEX">\({\upmu }\)</EquationSource> </InlineEquation>m P-well SPDM CMOS technological processes. The N transistors were fabricated in P-well and connected to GND via <InlineEquation ID="IEq2"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="41598_2025_14874_Article_IEq2.gif" Format="GIF" Height="16" Rendition="HTML" Resolution="72" Type="Linedraw" Width="24" /> </InlineMediaObject> <EquationSource Format="TEX">\(P^+\)</EquationSource> </InlineEquation>-well. The metal wires of <InlineEquation ID="IEq3"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="41598_2025_14874_Article_IEq3.gif" Format="GIF" Height="16" Rendition="HTML" Resolution="72" Type="Linedraw" Width="31" /> </InlineMediaObject> <EquationSource Format="TEX">\(V_{CC}\)</EquationSource> </InlineEquation> use <InlineEquation ID="IEq4"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="41598_2025_14874_Article_IEq4.gif" Format="GIF" Height="16" Rendition="HTML" Resolution="72" Type="Linedraw" Width="26" /> </InlineMediaObject> <EquationSource Format="TEX">\(N^+\)</EquationSource> </InlineEquation> substrate to contact <InlineEquation ID="IEq5"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="41598_2025_14874_Article_IEq3.gif" Format="GIF" Height="16" Rendition="HTML" Resolution="72" Type="Linedraw" Width="31" /> </InlineMediaObject> <EquationSource Format="TEX">\(V_{CC}\)</EquationSource> </InlineEquation>, to increase its anti-locking capability. An ESD protection circuit was designed at the input terminals, prohibiting the terminal of IC chip from being damaged by ESD stress. The performance of the device is superior to that of other similar products in the world.</p>

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Design and fabrication of 4 double input NAND gate chip with excellent electrical and physical performances

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  • 发表日期：

    2025年8月11日

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  • Lijun Zhang,
  • Wenqiang Dang,
  • Yu Lu,
  • Yongshun Wang

摘要

In order to improve the performances of 4 two-input NAND so that it can be better used in the aerospace application field and in harsh environments, 4 two-input NAND gate chips were designed and successfully fabricated in this paper, based on 1.2 \({\upmu }\) m P-well SPDM CMOS technological processes. The N transistors were fabricated in P-well and connected to GND via \(P^+\) -well. The metal wires of \(V_{CC}\) use \(N^+\) substrate to contact \(V_{CC}\) , to increase its anti-locking capability. An ESD protection circuit was designed at the input terminals, prohibiting the terminal of IC chip from being damaged by ESD stress. The performance of the device is superior to that of other similar products in the world.