Silicon has enabled advancements in semiconductor technology through miniaturization, but scaling challenges necessitate the exploration of new materials1. Two-dimensional (2D) materials, with their atomic thickness and high carrier mobility, offer a promising alternative2–5. Although significant progress has been made in wafer-scale growth6–8, high-performance field-effect transistors9–20 and circuits based on 2D materials21–23, achieving complementary metal–oxide–semiconductor (CMOS) integration remains a challenge. Here, we present a 2D one instruction set computer based on CMOS technology, leveraging the heterogeneous integration of large-area n-type MoS2 and p-type WSe2 field-effect transistors. By scaling the channel length, incorporating a high-κ gate dielectric and optimizing material growth and device postprocessing, we tailored the threshold voltages for both n- and p-type 2D field-effect transistors, achieving high drive currents and reduced subthreshold leakage. This enabled circuit operation below 3 V with an operating frequency of up to 25 kHz, which was constrained by parasitic capacitances, along with ultra-low power consumption in the picowatt range and a switching energy as low as approximately 100 pJ. Finally, we projected the performance of the one instruction set computer and benchmarked it against state-of-the-art silicon technology using an industry-standard SPICE-compatible BSIM-BULK model. This model was calibrated with experimental data that incorporate device-to-device variations. Although further advances are needed, this work marks a significant milestone in the application of 2D materials to microelectronics.
