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<p>Atomically thin two-dimensional (2D) semiconductors are promising candidates for next-generation electronics, which could effectively suppress short-channel effects and consequently reduce static power consumption. However, the lack of effective doping methods for 2D semiconductors remains a significant challenge, impeding the realization of homogeneous complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs). Here, we report the monolithic integration of wafer-scale homogeneous top-gated WSe<sub>2</sub> CMOS circuit arrays. The p-type and n-type doping methods could effectively modulate carrier polarity and concentration for WSe<sub>2</sub>, enabling the fabrication of wafer-scale CMOS inverter arrays via a proposed bilayer hard mask process. A representative CMOS inverter exhibits a voltage gain of up to 396 V/V, with a low static power consumption of ~ 30 pW and a noise margin exceeding 90%. Furthermore, more complex CMOS circuits, like XOR and a multiplexer (MUX), are successfully fabricated. This demonstration of homogeneous CMOS integration shows a promising strategy for the practical deployment of 2D semiconductors in low-power large-scale ICs.</p>

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Monolithic integration of p- and n-type doped 2D WSe2 for wafer-scale complementary logic circuits

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年5月25日

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  • Yan Hu,
  • Shicheng Zeng,
  • Yi Wang,
  • Jinshu Zhang,
  • Yuxuan Zhu,
  • Zhejia Zhang,
  • Xiangqi Dong,
  • Qicheng Sun,
  • Mingrui Ao,
  • Xinlong Guo,
  • Jieya Shang,
  • Yuexi Wang,
  • Chao Liu,
  • Yuchen Tian,
  • Haojie Chen,
  • Xinliu He,
  • Yufei Song,
  • Yue Zhang,
  • Sen Wang,
  • Junlong Shi,
  • Zhengjie Sun,
  • Jiahao Wang,
  • Jichao Li,
  • Liping Jiang,
  • Lin Wang,
  • Chao Zhu,
  • Zihan Xu,
  • Saifei Gou,
  • Yin Wang,
  • Yin Xia,
  • Xu Wang,
  • Zhengzong Sun,
  • Wenzhong Bao

摘要

Atomically thin two-dimensional (2D) semiconductors are promising candidates for next-generation electronics, which could effectively suppress short-channel effects and consequently reduce static power consumption. However, the lack of effective doping methods for 2D semiconductors remains a significant challenge, impeding the realization of homogeneous complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs). Here, we report the monolithic integration of wafer-scale homogeneous top-gated WSe2 CMOS circuit arrays. The p-type and n-type doping methods could effectively modulate carrier polarity and concentration for WSe2, enabling the fabrication of wafer-scale CMOS inverter arrays via a proposed bilayer hard mask process. A representative CMOS inverter exhibits a voltage gain of up to 396 V/V, with a low static power consumption of ~ 30 pW and a noise margin exceeding 90%. Furthermore, more complex CMOS circuits, like XOR and a multiplexer (MUX), are successfully fabricated. This demonstration of homogeneous CMOS integration shows a promising strategy for the practical deployment of 2D semiconductors in low-power large-scale ICs.