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<p>Recent progress in generative modeling has intensified the need for compact, energy-efficient hardware platforms. Yet, implementing image generation directly in hardware remains challenging due to the conflicting requirements of stochastic latent space sampling and deterministic decoding. Here, we show a unified hardware framework based on hafnium-oxide ferroelectric tunnel junctions (FTJs) that intrinsically support both functionalities within a single device array. Leveraging the CMOS- and VLSI-compatible fabrication of hafnia ferroelectrics, we realize dual-mode operation: random telegraph noise generation for controllable stochastic sampling, and high-fidelity vector–matrix multiplication enabled by non-volatile multi-level conductance states. Voltage and sampling-time tuning provide fine control over randomness and reliability, enabling high-quality image generation for tasks such as handwritten digit synthesis (MNIST) and high-resolution facial image generation (CelebA). Circuit-level demonstrations confirm stable performance over 10<sup>5</sup> cycles, surpassing prior hardware-based approaches and illustrating a viable route toward scalable, on-chip generative AI accelerators.</p>

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CMOS-compatible ferroelectric tunnel junctions integrate stochastic sampling and deterministic computing for image generation

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年5月8日

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  • Ryun-Han Koo,
  • Jonghyun Ko,
  • Wonjun Shin,
  • Sangwoo Ryu,
  • Jiseong Im,
  • Sung-Ho Park,
  • Joon Hwang,
  • Minsuk Song,
  • Youngchan Cho,
  • Jangsaeng Kim,
  • Gyuweon Jung,
  • Daewoong Kwon,
  • Jong-Ho Lee

摘要

Recent progress in generative modeling has intensified the need for compact, energy-efficient hardware platforms. Yet, implementing image generation directly in hardware remains challenging due to the conflicting requirements of stochastic latent space sampling and deterministic decoding. Here, we show a unified hardware framework based on hafnium-oxide ferroelectric tunnel junctions (FTJs) that intrinsically support both functionalities within a single device array. Leveraging the CMOS- and VLSI-compatible fabrication of hafnia ferroelectrics, we realize dual-mode operation: random telegraph noise generation for controllable stochastic sampling, and high-fidelity vector–matrix multiplication enabled by non-volatile multi-level conductance states. Voltage and sampling-time tuning provide fine control over randomness and reliability, enabling high-quality image generation for tasks such as handwritten digit synthesis (MNIST) and high-resolution facial image generation (CelebA). Circuit-level demonstrations confirm stable performance over 105 cycles, surpassing prior hardware-based approaches and illustrating a viable route toward scalable, on-chip generative AI accelerators.