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<p>The rapid expansion of AI models has intensified concerns over energy consumption. Analog in-memory computing with resistive memory offers a promising, energy-efficient alternative, yet its practical deployment is hindered by programming challenges and device non-idealities. Here, we propose a software-hardware co-design that trains randomly weighted resistive-memory neural networks via edge-pruning topology optimization. Software-wise, we tailor the network topology to extract high-performing sub-networks without precise weight tuning, enhancing robustness to device variations and reducing programming overhead. Hardware-wise, we harness the intrinsic stochasticity of resistive-memory electroforming to generate large-scale, low-cost random weights. Implemented on a 40 nm resistive memory chip, our co-design yields accuracy improvements of 17.3% and 19.9% on Fashion-MNIST and Spoken Digit, respectively, and a 9.8% precision-recall AUC improvement on DRIVE, while reducing energy consumption by 78.3%, 67.9%, and 99.7%. We further demonstrate broad applicability across analog memory technologies and scalability to ResNet-50 on ImageNet-100.</p>

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Pruning random resistive memory for optimizing analog AI

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年1月10日

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  • Yi Li,
  • Songqi Wang,
  • Yaping Zhao,
  • Shaocong Wang,
  • Bo Wang,
  • Woyu Zhang,
  • Yangu He,
  • Ning Lin,
  • Binbin Cui,
  • Xi Chen,
  • Shiming Zhang,
  • Hao Jiang,
  • Peng Lin,
  • Xumeng Zhang,
  • Feng Zhang,
  • Xiaojuan Qi,
  • Zhongrui Wang,
  • Xiaoxin Xu,
  • Dashan Shang,
  • Qi Liu,
  • Han Wang,
  • Kwang-Ting Cheng,
  • Ming Liu

摘要

The rapid expansion of AI models has intensified concerns over energy consumption. Analog in-memory computing with resistive memory offers a promising, energy-efficient alternative, yet its practical deployment is hindered by programming challenges and device non-idealities. Here, we propose a software-hardware co-design that trains randomly weighted resistive-memory neural networks via edge-pruning topology optimization. Software-wise, we tailor the network topology to extract high-performing sub-networks without precise weight tuning, enhancing robustness to device variations and reducing programming overhead. Hardware-wise, we harness the intrinsic stochasticity of resistive-memory electroforming to generate large-scale, low-cost random weights. Implemented on a 40 nm resistive memory chip, our co-design yields accuracy improvements of 17.3% and 19.9% on Fashion-MNIST and Spoken Digit, respectively, and a 9.8% precision-recall AUC improvement on DRIVE, while reducing energy consumption by 78.3%, 67.9%, and 99.7%. We further demonstrate broad applicability across analog memory technologies and scalability to ResNet-50 on ImageNet-100.