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<p>The practicality of memristor-based computation-in-memory (CIM) systems is limited by the specific hardware design and the manual parameters tuning process. Here, we introduce a software-hardware co-development approach to improve the flexibility and efficiency of the CIM system. The hardware component supports flexible dataflow, and facilitates various weight and input mappings. The software aspect enables automatic model placement and multiple efficient optimizations. The proposed optimization methods can enhance the robustness of model weights against hardware nonidealities during the training phase and automatically identify the optimal hardware parameters to suppress the impacts of analogue computing noise during the inference phase. Utilizing the full-stack system, we experimentally demonstrate six neural network models across four distinct tasks on the hardware automatically. With the help of optimization methods, we observe a 4.76% accuracy improvement for ResNet-32 during the training phase, and a 3.32% to 9.45% improvement across the six models during the on-chip inference phase.</p>

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A full-stack memristor-based computation-in-memory system with software-hardware co-development

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2025年3月3日

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  • Ruihua Yu,
  • Ze Wang,
  • Qi Liu,
  • Bin Gao,
  • Zhenqi Hao,
  • Tao Guo,
  • Sanchuan Ding,
  • Junyang Zhang,
  • Qi Qin,
  • Dong Wu,
  • Peng Yao,
  • Qingtian Zhang,
  • Jianshi Tang,
  • He Qian,
  • Huaqiang Wu

摘要

The practicality of memristor-based computation-in-memory (CIM) systems is limited by the specific hardware design and the manual parameters tuning process. Here, we introduce a software-hardware co-development approach to improve the flexibility and efficiency of the CIM system. The hardware component supports flexible dataflow, and facilitates various weight and input mappings. The software aspect enables automatic model placement and multiple efficient optimizations. The proposed optimization methods can enhance the robustness of model weights against hardware nonidealities during the training phase and automatically identify the optimal hardware parameters to suppress the impacts of analogue computing noise during the inference phase. Utilizing the full-stack system, we experimentally demonstrate six neural network models across four distinct tasks on the hardware automatically. With the help of optimization methods, we observe a 4.76% accuracy improvement for ResNet-32 during the training phase, and a 3.32% to 9.45% improvement across the six models during the on-chip inference phase.