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<p>The rapid growth of IoT devices and data in edge computing applications has created a pressing need for efficient lossless compression of end-edge data. The Lempel-Ziv-Welch (LZW) algorithm, widely used in these scenarios, faces bottlenecks in compression speed due to its inherent data dependency. Unlike existing multi-cycle architectures, we propose PLZW, a pipeline-based LZW acceleration architecture with three novel mechanisms: a data bypass mechanism that allows data to pass directly between pipeline stages, minimizing stalls; a multi-level caching mechanism to reduce pipeline stalls caused by long dictionary update times; and a hash prediction mechanism to improve dictionary lookup hit rates and reduce stall frequency. Our field-programmable gate array (FPGA) implementation demonstrates a 2.5<InlineEquation ID="IEq1"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="44443_2025_243_Article_IEq1.gif" Format="GIF" Height="13" Rendition="HTML" Resolution="72" Type="Linedraw" Width="19" /> </InlineMediaObject> <EquationSource Format="TEX">\(\times \)</EquationSource> <EquationSource Format="MATHML"><math> <mo>×</mo> </math></EquationSource> </InlineEquation> speedup over existing state-of-the-art methods while maintaining competitive power consumption, resource utilization, and compression ratio. Furthermore, the resource utilization remains below 1% of total FPGA resources, and the proposed mechanisms improve the dictionary first-hit rate by 35.8%. This work offers a high-speed, lightweight, generic solution for lossless compression of end-edge data. PLZW provides a reference implementation for optimizing hardware-based data compression in real-time and resource-constrained applications.</p>

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PLZW: FPGA-based Pipelined LZW for lossless compression of edge data

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年9月24日

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  • Xiao Liu,
  • Akram Y. Sarhan,
  • Shubo Liu,
  • Zhaohui Cai,
  • Guoqing Tu,
  • Faisal S. Alsubaei,
  • Yousef S. Alsahafi

摘要

The rapid growth of IoT devices and data in edge computing applications has created a pressing need for efficient lossless compression of end-edge data. The Lempel-Ziv-Welch (LZW) algorithm, widely used in these scenarios, faces bottlenecks in compression speed due to its inherent data dependency. Unlike existing multi-cycle architectures, we propose PLZW, a pipeline-based LZW acceleration architecture with three novel mechanisms: a data bypass mechanism that allows data to pass directly between pipeline stages, minimizing stalls; a multi-level caching mechanism to reduce pipeline stalls caused by long dictionary update times; and a hash prediction mechanism to improve dictionary lookup hit rates and reduce stall frequency. Our field-programmable gate array (FPGA) implementation demonstrates a 2.5 \(\times \) × speedup over existing state-of-the-art methods while maintaining competitive power consumption, resource utilization, and compression ratio. Furthermore, the resource utilization remains below 1% of total FPGA resources, and the proposed mechanisms improve the dictionary first-hit rate by 35.8%. This work offers a high-speed, lightweight, generic solution for lossless compression of end-edge data. PLZW provides a reference implementation for optimizing hardware-based data compression in real-time and resource-constrained applications.