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<p>In modern communication systems exchange vast amounts of information daily. Automobiles use sophisticated technologies that demand reliable, simple, and fast communication. Noise inevitably affects the communication channel and can corrupt transmitted data. Therefore, engineers must detect and correct errors. We present Improved Hamming Codes (IHC), which require fewer parity bits than CRC codes and detect and correct single-bit errors in the CAN protocol. The CAN protocol typically identifies transmission errors using CRC codes and always includes 15 redundancy bits, regardless of the input data size. In this study, we introduce IHC, which offers lower redundancy. Depending on the input data, IHC reduces the number of parity bits and increases the CAN protocol’s frame rate. We synthesize the proposed technique using the Xilinx Nexys Artix-7 FPGA kit. Simulation results demonstrate the outputs of the IHC encoder and decoder, both with and without errors, highlighting IHC as a more effective choice for single-bit error correction in CAN systems. The Improved Hamming Code Architecture uses 10.242 nW leakage, 15726.365 nW dynamic, and 15736.607 nW total power when synthesized with Cadence Software at 180&#xa0;nm technology, compared to the traditional CRC method.</p>

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Implementation of improved hamming code for reliable CAN protocol on FPGA

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年4月20日

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  • H. S. Nagarathna,
  • K. R. Ramesh Kumar

摘要

In modern communication systems exchange vast amounts of information daily. Automobiles use sophisticated technologies that demand reliable, simple, and fast communication. Noise inevitably affects the communication channel and can corrupt transmitted data. Therefore, engineers must detect and correct errors. We present Improved Hamming Codes (IHC), which require fewer parity bits than CRC codes and detect and correct single-bit errors in the CAN protocol. The CAN protocol typically identifies transmission errors using CRC codes and always includes 15 redundancy bits, regardless of the input data size. In this study, we introduce IHC, which offers lower redundancy. Depending on the input data, IHC reduces the number of parity bits and increases the CAN protocol’s frame rate. We synthesize the proposed technique using the Xilinx Nexys Artix-7 FPGA kit. Simulation results demonstrate the outputs of the IHC encoder and decoder, both with and without errors, highlighting IHC as a more effective choice for single-bit error correction in CAN systems. The Improved Hamming Code Architecture uses 10.242 nW leakage, 15726.365 nW dynamic, and 15736.607 nW total power when synthesized with Cadence Software at 180 nm technology, compared to the traditional CRC method.