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<p>2D materials have the potential to extend and augment the CMOS scaling roadmap. However, upscaling from lab-based demonstrators to 300&#xa0;mm-compatible integration modules presents unique challenges. In this work, we address these challenges through a 2D FET process flow developed within imec’s 300&#xa0;mm Si pilot line. FETs with monolayer 2D transition metal dichalcogenide (TMDC) channels are fabricated, and the flow serves as a research vehicle to advance 300&#xa0;mm-compatible integration modules, including TMDC growth, transfer, cleaning, gate stack deposition, and contact optimization. Key integration challenges arising from the weakly van der Waals-bonded 2D materials are identified, and the motivation behind specific process choices is discussed in the context of fab-specific contamination control. The processing is followed by a rigorous electrical characterization with dedicated test structures to evaluate the FET performance metrics, gate stack scalability, device yield, variability, reliability and stability. This paper provides, for the first time, a comprehensive and systematic description of our 300&#xa0;mm fab-compatible integration flow for planar 2D FETs, broken down into its individual process modules and supported by a full electrical evaluation.</p>

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Integration and electrical evaluation of WS2 and MoS2 fets in a 300 mm pilot line

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年2月1日

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  • T Schram,
  • Q Smets,
  • A Opdebeeck,
  • S Ghosh,
  • B Groven,
  • P Kumar,
  • H M Medina,
  • D Cott,
  • J.-F deMarneffe,
  • H Dongre,
  • A Kruv,
  • L Panarella,
  • L F Pinotti,
  • P Morin,
  • G. S. Kar,
  • C. J. Lockhart de la Rosa

摘要

2D materials have the potential to extend and augment the CMOS scaling roadmap. However, upscaling from lab-based demonstrators to 300 mm-compatible integration modules presents unique challenges. In this work, we address these challenges through a 2D FET process flow developed within imec’s 300 mm Si pilot line. FETs with monolayer 2D transition metal dichalcogenide (TMDC) channels are fabricated, and the flow serves as a research vehicle to advance 300 mm-compatible integration modules, including TMDC growth, transfer, cleaning, gate stack deposition, and contact optimization. Key integration challenges arising from the weakly van der Waals-bonded 2D materials are identified, and the motivation behind specific process choices is discussed in the context of fab-specific contamination control. The processing is followed by a rigorous electrical characterization with dedicated test structures to evaluate the FET performance metrics, gate stack scalability, device yield, variability, reliability and stability. This paper provides, for the first time, a comprehensive and systematic description of our 300 mm fab-compatible integration flow for planar 2D FETs, broken down into its individual process modules and supported by a full electrical evaluation.