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<p>The rising need for high-performance and energy-efficient VLSI systems has highlighted the limitations of CMOS technology at nanoscale dimensions, particularly because of the increased leakage current, short-channel effects, and reduced power efficiency. Carbon Nanotube Field-Effect Transistors (CNTFETs) offer a promising alternative because of their near-ballistic transport, high carrier mobility, and strong electrostatic control. The research work evaluates logic gates, adders, encoders, decoders, multiplexers, and flip-flops implemented using the Stanford 32&#xa0;nm CNTFET model in Cadence Virtuoso. CMOS baselines at 90&#xa0;nm were used to provide relative technology-behavior insights. Detailed transient, DC, and AC simulations were conducted to extract delay, power, and PDP. Based on the simulation results, CNTFET implementations with respect to conventional CMOS technology demonstrated power reductions ranging from approximately 45% to 69% and delay improvements between 21% and 67%, depending on the circuit complexity. These results indicate that CNTFET technology offers significant potential for low-power and high-speed digital designs at advanced technology nodes, making it a strong for memory circuits, and future scalable nano-electronics.</p>

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Exploration of digital building blocks in 32 nm CNTFET technology for scalable VLSI applications

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年1月16日

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  • Jayakrishna Padala,
  • Kishorekumar Kamarajugadda,
  • Pavani Movva

摘要

The rising need for high-performance and energy-efficient VLSI systems has highlighted the limitations of CMOS technology at nanoscale dimensions, particularly because of the increased leakage current, short-channel effects, and reduced power efficiency. Carbon Nanotube Field-Effect Transistors (CNTFETs) offer a promising alternative because of their near-ballistic transport, high carrier mobility, and strong electrostatic control. The research work evaluates logic gates, adders, encoders, decoders, multiplexers, and flip-flops implemented using the Stanford 32 nm CNTFET model in Cadence Virtuoso. CMOS baselines at 90 nm were used to provide relative technology-behavior insights. Detailed transient, DC, and AC simulations were conducted to extract delay, power, and PDP. Based on the simulation results, CNTFET implementations with respect to conventional CMOS technology demonstrated power reductions ranging from approximately 45% to 69% and delay improvements between 21% and 67%, depending on the circuit complexity. These results indicate that CNTFET technology offers significant potential for low-power and high-speed digital designs at advanced technology nodes, making it a strong for memory circuits, and future scalable nano-electronics.