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<p>This paper proposes a low-power Arithmetic Logic Unit (ALU) architecture that integrates a Hybrid Clock Gating (HCG) technique combining instruction-aware and operand-aware control mechanisms. Theproposeddesignselectivelydisablestheclocksignaltoarithmeticunits, such as the adder, when no meaningful computation is scheduled or when operand values remain unchanged across cycles. A hierarchical control unit is employed to decode instructions and monitor operand transitions, enabling fine-grained clock gating through a dedicated gating logic block. This method significantly reduces unnecessary switching activity and dynamic power consumption without compromising performance. The ALU was synthesized and evaluated using Xilinx Vivado 2022.1. Experimental results demonstrate that the proposed HCG-ALU achieves up to 52.22% dynamic power reduction compared to traditional ALU architecture, making the proposed HCG-ALU suitable for power-sensitive applications in embedded processors and RISC-V based systems. It achieved a 52.2% reduction in dynamic power, with a maximum delay of 6.8&#xa0;ns and a cell area of 3687 µm<sup>2</sup>, compared to a baseline ALU.</p>

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Low power ALU design using hybrid clock gating: architecture, analysis, and experimental evaluation

  • 期刊论文

  • 发表日期：

    2025年9月8日

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  • V. Priyadarshini,
  • M. Kamaraju,
  • U. V. RatnaKumari

摘要

This paper proposes a low-power Arithmetic Logic Unit (ALU) architecture that integrates a Hybrid Clock Gating (HCG) technique combining instruction-aware and operand-aware control mechanisms. Theproposeddesignselectivelydisablestheclocksignaltoarithmeticunits, such as the adder, when no meaningful computation is scheduled or when operand values remain unchanged across cycles. A hierarchical control unit is employed to decode instructions and monitor operand transitions, enabling fine-grained clock gating through a dedicated gating logic block. This method significantly reduces unnecessary switching activity and dynamic power consumption without compromising performance. The ALU was synthesized and evaluated using Xilinx Vivado 2022.1. Experimental results demonstrate that the proposed HCG-ALU achieves up to 52.22% dynamic power reduction compared to traditional ALU architecture, making the proposed HCG-ALU suitable for power-sensitive applications in embedded processors and RISC-V based systems. It achieved a 52.2% reduction in dynamic power, with a maximum delay of 6.8 ns and a cell area of 3687 µm2, compared to a baseline ALU.