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<p>A novel double-gate carrier-storage floating deep p-region IGBT (DGCS-FD-IGBT) is proposed to optimize the trade-off between electromagnetic interference (EMI) and turn-on energy loss during low-current switching. A carrier storage layer is introduced beneath the p-base to increase the carrier concentration in the drift region and reduce the on-state voltage drop. In addition, two symmetrical dummy gate trenches are embedded inside the floating p-region and electrically connected to the main gate via an upper polysilicon layer, thereby dividing the the floating p-region into three sub-regions. This configuration effectively suppresses the hole accumulation near the main gate trench and reduces the displacement current. Simulation results show that the overshoot peaks of ICE and VGE decrease by 30% and 10.2%, while the peak values of <i>dI</i><sub>CE</sub>/<i>dt</i>, <i>dV</i><sub>GE</sub>/dt, and <i>dV</i><sub>KA</sub>/<i>dt</i> are reduced by 36.3%, 35.3%, and 10.6%, respectively. These improvements demonstrate that the proposed structure suppresses EMI and enhances the EMI-turn-on loss trade-off. Consequently, the DGCS-FD-IGBT can mitigate both gate-loop oscillations and conducted EMI in applications such as electric vehicle traction inverters and grid-connected converters, where devices frequently operate at light-load or discontinuous currents. By improving the intrinsic EMI–loss trade-off at the device level, the proposed structure helps system designers relax gate resistance margins and filter requirements while maintaining high efficiency and compliance with electromagnetic compatibility standards.</p>

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Carrier-storage floating p-region IGBT for EMI suppression

  • 期刊论文

  • 发表日期：

    2026年2月26日

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  • Yu Xie,
  • Quanyuan Feng,
  • Yixuanzhe Zhou

摘要

A novel double-gate carrier-storage floating deep p-region IGBT (DGCS-FD-IGBT) is proposed to optimize the trade-off between electromagnetic interference (EMI) and turn-on energy loss during low-current switching. A carrier storage layer is introduced beneath the p-base to increase the carrier concentration in the drift region and reduce the on-state voltage drop. In addition, two symmetrical dummy gate trenches are embedded inside the floating p-region and electrically connected to the main gate via an upper polysilicon layer, thereby dividing the the floating p-region into three sub-regions. This configuration effectively suppresses the hole accumulation near the main gate trench and reduces the displacement current. Simulation results show that the overshoot peaks of ICE and VGE decrease by 30% and 10.2%, while the peak values of dICE/dt, dVGE/dt, and dVKA/dt are reduced by 36.3%, 35.3%, and 10.6%, respectively. These improvements demonstrate that the proposed structure suppresses EMI and enhances the EMI-turn-on loss trade-off. Consequently, the DGCS-FD-IGBT can mitigate both gate-loop oscillations and conducted EMI in applications such as electric vehicle traction inverters and grid-connected converters, where devices frequently operate at light-load or discontinuous currents. By improving the intrinsic EMI–loss trade-off at the device level, the proposed structure helps system designers relax gate resistance margins and filter requirements while maintaining high efficiency and compliance with electromagnetic compatibility standards.