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<p>Second-order generalized integrator phase-locked loops are widely used in grid-connected inverters. However, the presence of DC offset in the grid voltage can lead to insufficient filtering, causing fluctuations in the input signal detection. To address this challenge, this paper introduces an improved second/third-order hybrid generalized integrator structure. This enhanced design separates positive and negative sequence voltages and includes a DC component suppression module, enhancing the ability of the phase-locked loop to suppress DC voltage offset and ensure accurate locking of the grid voltage phase. Moreover, the proposed PLL incorporates linear active disturbance rejection control (LADRC) instead of the traditional PI control loop. This modification provides stronger anti-interference capabilities and effectively combats nonlinear disturbances without requiring an accurate model, making it suitable for non-ideal grid conditions. Simulations and experimental studies conducted on MATLAB and dSPACE platforms confirm that the proposed PLL effectively filters out DC components under non-ideal grid conditions and exhibits both excellent anti-interference performance and rapid dynamic response due to the application of LADRC.</p>

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Enhanced second/third-order hybrid generalized integrator phase-locked loops with linear active disturbance rejection control

  • 期刊论文

  • 发表日期：

    2025年1月9日

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  • Wei Luo,
  • Hongyi Zhang,
  • Yue Lian

摘要

Second-order generalized integrator phase-locked loops are widely used in grid-connected inverters. However, the presence of DC offset in the grid voltage can lead to insufficient filtering, causing fluctuations in the input signal detection. To address this challenge, this paper introduces an improved second/third-order hybrid generalized integrator structure. This enhanced design separates positive and negative sequence voltages and includes a DC component suppression module, enhancing the ability of the phase-locked loop to suppress DC voltage offset and ensure accurate locking of the grid voltage phase. Moreover, the proposed PLL incorporates linear active disturbance rejection control (LADRC) instead of the traditional PI control loop. This modification provides stronger anti-interference capabilities and effectively combats nonlinear disturbances without requiring an accurate model, making it suitable for non-ideal grid conditions. Simulations and experimental studies conducted on MATLAB and dSPACE platforms confirm that the proposed PLL effectively filters out DC components under non-ideal grid conditions and exhibits both excellent anti-interference performance and rapid dynamic response due to the application of LADRC.