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<p>This paper assesses the performance of the RISCV-EC, a soft processor featuring a 5-stage, multi-cycle, non-pipelined architecture that executes each instruction in its entirety before proceeding to the next one. The design processes instructions sequentially, issuing a single instruction per cycle. The study benchmarks the RISCV-EC against other processors by analyzing its efficiency, execution speed, and overall performance across a range of computational workloads. By methodically increasing the number of iterations, we estimate the execution time of the Fibonacci sequence algorithm. For a rigorous comparison, the soft processor was implemented on a Xilinx Zynq-7000 SoC FPGA and configured to run at the same clock frequency as the other processors, thus eliminating any overclocking-related biases. Experimental results show that although the RISCV-EC executes fewer instructions and exhibits competitive architectural efficiency, it consumes more dynamic power than the ATMEGA328P AVR processor under the same benchmark conditions. Furthermore, the execution of algorithms for the Fibonacci sequence, matrix multiplication, and RGB-to-HSL conversion requires fewer instructions on the RISCV-EC compared to its counterparts. These findings underscore the potential of the RISCV-EC for energy-efficient edge computing, particularly in scenarios with limited resources.</p>

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Evaluating the RISCV-EC: A Comparative Analysis of Instruction Efficiency and Power Performance for Edge Computing

  • 期刊论文

  • 发表日期：

    2025年8月25日

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  • Víctor Asanza,
  • Guillermo Montesdeoca,
  • Rebeca Estrada,
  • Dagoberto Mayorca-Torres,
  • Moad Hicham Safhi,
  • Diego H. Peluffo-Ordóñez

摘要

This paper assesses the performance of the RISCV-EC, a soft processor featuring a 5-stage, multi-cycle, non-pipelined architecture that executes each instruction in its entirety before proceeding to the next one. The design processes instructions sequentially, issuing a single instruction per cycle. The study benchmarks the RISCV-EC against other processors by analyzing its efficiency, execution speed, and overall performance across a range of computational workloads. By methodically increasing the number of iterations, we estimate the execution time of the Fibonacci sequence algorithm. For a rigorous comparison, the soft processor was implemented on a Xilinx Zynq-7000 SoC FPGA and configured to run at the same clock frequency as the other processors, thus eliminating any overclocking-related biases. Experimental results show that although the RISCV-EC executes fewer instructions and exhibits competitive architectural efficiency, it consumes more dynamic power than the ATMEGA328P AVR processor under the same benchmark conditions. Furthermore, the execution of algorithms for the Fibonacci sequence, matrix multiplication, and RGB-to-HSL conversion requires fewer instructions on the RISCV-EC compared to its counterparts. These findings underscore the potential of the RISCV-EC for energy-efficient edge computing, particularly in scenarios with limited resources.