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<p>This paper presents a hardware-aware synchronous PWM strategy for single-inverter drives operating in overmodulation. The method derives closed-form relations between the switching angles and the modulation index and applies them as rotor-synchronized patterns. Patterns are precomputed into a compact lookup table (LUT) with light online refinement and are issued via direct memory access (DMA), decoupling timing from the CPU and eliminating scheduling-induced timing jitter. Unlike selective harmonic elimination/minimization pipelines, the proposed strategy targets harmonic reduction and total harmonic distortion (THD) minimization under practical constraints, explicitly accounting for dead time, interrupt latency, and timer quantization to ensure deployability on embedded controllers. Harmonic analysis guides the angle design, and the resulting patterns maintain waveform symmetry while reducing ripple. Bench and simulation studies show total harmonic distortion drops from 33% to 15% at high modulation indices, with lower processing overhead and stable tracking across wide speed–load ranges. Robustness tests with intentional angle offsets indicate graceful degradation and preserved timing alignment. The approach provides a deterministic, low-latency control path for high-speed motor drives and can be adopted on automotive-grade MCUs without architectural changes.</p>

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A Practical Synchronous PWM Design for Reducing THD in Overmodulated Single-Inverter Drives

  • 期刊论文

  • 发表日期：

    2026年2月25日

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  • Jun Imaoka,
  • Masayoshi Yamamoto,
  • Chaeduck Chon

摘要

This paper presents a hardware-aware synchronous PWM strategy for single-inverter drives operating in overmodulation. The method derives closed-form relations between the switching angles and the modulation index and applies them as rotor-synchronized patterns. Patterns are precomputed into a compact lookup table (LUT) with light online refinement and are issued via direct memory access (DMA), decoupling timing from the CPU and eliminating scheduling-induced timing jitter. Unlike selective harmonic elimination/minimization pipelines, the proposed strategy targets harmonic reduction and total harmonic distortion (THD) minimization under practical constraints, explicitly accounting for dead time, interrupt latency, and timer quantization to ensure deployability on embedded controllers. Harmonic analysis guides the angle design, and the resulting patterns maintain waveform symmetry while reducing ripple. Bench and simulation studies show total harmonic distortion drops from 33% to 15% at high modulation indices, with lower processing overhead and stable tracking across wide speed–load ranges. Robustness tests with intentional angle offsets indicate graceful degradation and preserved timing alignment. The approach provides a deterministic, low-latency control path for high-speed motor drives and can be adopted on automotive-grade MCUs without architectural changes.