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<p>This paper proposes an enhanced phase-locked loop (PLL) algorithm, derived from the second-order generalized integrator phase-locked loop (SOGI-PLL), to address the prevalent challenges of DC offset and frequency variations in power grids. The proposed approach integrates a fixed-frequency SOGI module into the front-stage SOGI, effectively suppressing DC offset while simplifying parameter tuning. Simultaneously, the back-stage PLL incorporates gain and over-phase compensation mechanisms. Furthermore, the integration link of the proportional-integral controller is optimized to minimize steady-state errors during frequency transients and accelerate the dynamic response. The design of the improved structure and its corresponding parameters are guided by Bode plot analysis and small-signal model derivation. The proposed single-phase PLL demonstrates exceptional performance, effectively eliminating steady-state errors under DC offset and frequency ramp conditions while exhibiting robust dynamic performance and stability. The superiority of this method is validated through comprehensive Matlab/Simulink simulations and experimental results.</p>

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An Improved SOGI-PLL for DC Offsets and Frequency Ramps

  • 期刊论文

  • 发表日期：

    2025年6月5日

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  • Yingying Zhang,
  • Yueteng Shen,
  • Tonghua Wang,
  • Tingli Cheng,
  • Zhiwei Chen

摘要

This paper proposes an enhanced phase-locked loop (PLL) algorithm, derived from the second-order generalized integrator phase-locked loop (SOGI-PLL), to address the prevalent challenges of DC offset and frequency variations in power grids. The proposed approach integrates a fixed-frequency SOGI module into the front-stage SOGI, effectively suppressing DC offset while simplifying parameter tuning. Simultaneously, the back-stage PLL incorporates gain and over-phase compensation mechanisms. Furthermore, the integration link of the proportional-integral controller is optimized to minimize steady-state errors during frequency transients and accelerate the dynamic response. The design of the improved structure and its corresponding parameters are guided by Bode plot analysis and small-signal model derivation. The proposed single-phase PLL demonstrates exceptional performance, effectively eliminating steady-state errors under DC offset and frequency ramp conditions while exhibiting robust dynamic performance and stability. The superiority of this method is validated through comprehensive Matlab/Simulink simulations and experimental results.