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<p>With the growing demand for AI accelerators, high-density semiconductor packaging technologies enabling vertical and horizontal expansion of high-capacity memory are advancing rapidly. However, multilayer stacking and increased chip size have significantly intensified warpage issues during fabrication and use. Warpage is a major cause of stacking misalignment, reduced solder joint reliability, and increased complexity in subsequent processes. In flip-chip packages in particular, time-dependent warpage following thermocompression bonding presents an additional challenge. In this study, we propose a deep learning-based predictive model trained on limited experimental warpage data, using chip thickness, chip size, substrate thickness, and temperature conditions as input variables. Furthermore, we present a methodology for comprehensively predicting time-dependent warpage mitigation behavior, demonstrating the potential for rapid design optimization and improved process stability.</p> Graphical abstract <p>A deep learning-based framework for predicting warpage behavior in semiconductor packages. The model utilizes structural and environmental parameters to accurately predict temperature- and time-dependent warpage, enabling rapid design optimization with limited experimental data.</p> <p></p>

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Deep learning-based prediction of warpage behavior in semiconductor packaging

  • 期刊论文

  • 发表日期：

    2026年5月22日

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  • Jaehee Shin,
  • Jinhyoung Park

摘要

With the growing demand for AI accelerators, high-density semiconductor packaging technologies enabling vertical and horizontal expansion of high-capacity memory are advancing rapidly. However, multilayer stacking and increased chip size have significantly intensified warpage issues during fabrication and use. Warpage is a major cause of stacking misalignment, reduced solder joint reliability, and increased complexity in subsequent processes. In flip-chip packages in particular, time-dependent warpage following thermocompression bonding presents an additional challenge. In this study, we propose a deep learning-based predictive model trained on limited experimental warpage data, using chip thickness, chip size, substrate thickness, and temperature conditions as input variables. Furthermore, we present a methodology for comprehensively predicting time-dependent warpage mitigation behavior, demonstrating the potential for rapid design optimization and improved process stability.

Graphical abstract

A deep learning-based framework for predicting warpage behavior in semiconductor packages. The model utilizes structural and environmental parameters to accurately predict temperature- and time-dependent warpage, enabling rapid design optimization with limited experimental data.