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Introduction <p>Transistor count is a critical circuit-level metric, as it directly influences power consumption, propagation delay, leakage, and overall design complexity in VLSI systems. In Electronic Design Automation (EDA) workflows, variations in transistor count significantly affect simulation time, memory usage, and convergence behavior due to the increased number of nodes and nonlinear equations involved.</p> Background <p>Consequently, accurate transistor quantification and performance modeling are essential for efficient design exploration and scalable verification, which remain insufficiently addressed in existing literature.</p> Methodology <p>This work presents an integrated simulation-Machine Learning–Interpretability pipeline for JK flip-flop circuits, termed as ’DDX-JK’. A structured dataset is systematically constructed from validated CMOS transistor-level simulations across multiple JK flip-flop configurations with varying transistor counts, which ensures that model training is grounded in realistic device-level behavior. Using this simulation-derived dataset, a machine learning classifier is trained to predict transistor sizing and associated performance characteristics for unseen circuit configurations, thereby reducing the reliance on exhaustive device-level simulations during early-stage design exploration.</p> Results <p>Experimental results demonstrate the robustness of the proposed approach in terms of prediction confidence, residual error behavior, and comparative performance trends across different configurations. Furthermore, explainability-driven visualizations, including violin, beeswarm, and Pareto plots, are employed to analyze feature importance and parameter-performance relationships, which supports transparent and informed circuit-level decision-making. The proposed ML model approximates the nonlinear mapping from transistor sizing parameters to JK flip-flop delay, power, and area metrics, which enables rapid exploration of the delay-power-area trade-off space without repeated transistor-level simulations. The proposed methodology is applicable to high-speed and low-power digital systems such as counters, registers, and memory elements in modern VLSI designs.</p>

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DDX-JK: a data-driven and explainable machine learning framework for reducing circuit simulation overhead in CMOS JK flip-flop designs

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年5月14日

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  • Arjun Sunil Rao,
  • R. Roopalakshmi,
  • Samrat Sharma,
  • Samana Nagendran,
  • Prachita Singal,
  • Aditi Javeri,
  • Nandana Kamath,
  • Adithya Sriraman

摘要

Introduction

Transistor count is a critical circuit-level metric, as it directly influences power consumption, propagation delay, leakage, and overall design complexity in VLSI systems. In Electronic Design Automation (EDA) workflows, variations in transistor count significantly affect simulation time, memory usage, and convergence behavior due to the increased number of nodes and nonlinear equations involved.

Background

Consequently, accurate transistor quantification and performance modeling are essential for efficient design exploration and scalable verification, which remain insufficiently addressed in existing literature.

Methodology

This work presents an integrated simulation-Machine Learning–Interpretability pipeline for JK flip-flop circuits, termed as ’DDX-JK’. A structured dataset is systematically constructed from validated CMOS transistor-level simulations across multiple JK flip-flop configurations with varying transistor counts, which ensures that model training is grounded in realistic device-level behavior. Using this simulation-derived dataset, a machine learning classifier is trained to predict transistor sizing and associated performance characteristics for unseen circuit configurations, thereby reducing the reliance on exhaustive device-level simulations during early-stage design exploration.

Results

Experimental results demonstrate the robustness of the proposed approach in terms of prediction confidence, residual error behavior, and comparative performance trends across different configurations. Furthermore, explainability-driven visualizations, including violin, beeswarm, and Pareto plots, are employed to analyze feature importance and parameter-performance relationships, which supports transparent and informed circuit-level decision-making. The proposed ML model approximates the nonlinear mapping from transistor sizing parameters to JK flip-flop delay, power, and area metrics, which enables rapid exploration of the delay-power-area trade-off space without repeated transistor-level simulations. The proposed methodology is applicable to high-speed and low-power digital systems such as counters, registers, and memory elements in modern VLSI designs.