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<p>Shrinking CMOS devices face fundamental scaling limitations, including weakened electrostatic control and increased leakage currents, which in turn drive the exploration of alternative, non-charge-transport computing paradigms. Quantum-dot Cellular Automata (QCA) offers a compelling alternative by encoding logic in cell polarisation, promising ultra-low energy and extreme density. This work introduces single-layer QCA architectures for the full adder (QCAFA) and carry-save adder (CSA) that explicitly minimise delay, area, and cell complexity. The designs exploit clock-aware majority/inverter networks and layout regularity to eliminate multilayer crossovers and reduce routing congestion, enabling compact, pipeline-friendly arithmetic blocks suitable for ALUs, multipliers, and MAC units. Using QCADesigner 2.0.3 and QCADesigner-E, the proposed QCAFA achieves 46 cells with 0.04&#xa0;μm² area, 0.25 clock-cycle latency, and markedly reduced quantum cost, representing a 34.29% cell reduction relative to strong recent baselines. Likewise, the CSA requires only 424 cells within 0.56&#xa0;μm², delivering an 18.62% reduction in cell count against its best-known counterpart while sustaining 1.75 clock-cycle latency. Energy-dissipation analysis indicates low total/average energies (QCAFA: 1.31/1.10&#xa0;eV; CSA: 3.66/3.50&#xa0;eV), and temperature sweeps confirm stable output polarisation across 1–7&#xa0;K, underscoring robustness under canonical QCA operating conditions. Comprehensive benchmarking against state-of-the-art single and multilayer designs verifies consistent gains in cell count, area utilisation, quantum cost, and delay. By uniting single-layer manufacturability with system-level efficiency, these adders advance QCA from component-level novelty toward practical nanoscale arithmetic fabrics, charting a credible pathway for energy-efficient, densely integrated post-CMOS computing.</p>

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Compact and energy-efficient QCA architectures for full adder and carry-save adder: single-layer designs optimised for nanoscale circuits

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  • 发表日期：

    2025年10月30日

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  • Mohammad Abdullah-Al-Shafi

摘要

Shrinking CMOS devices face fundamental scaling limitations, including weakened electrostatic control and increased leakage currents, which in turn drive the exploration of alternative, non-charge-transport computing paradigms. Quantum-dot Cellular Automata (QCA) offers a compelling alternative by encoding logic in cell polarisation, promising ultra-low energy and extreme density. This work introduces single-layer QCA architectures for the full adder (QCAFA) and carry-save adder (CSA) that explicitly minimise delay, area, and cell complexity. The designs exploit clock-aware majority/inverter networks and layout regularity to eliminate multilayer crossovers and reduce routing congestion, enabling compact, pipeline-friendly arithmetic blocks suitable for ALUs, multipliers, and MAC units. Using QCADesigner 2.0.3 and QCADesigner-E, the proposed QCAFA achieves 46 cells with 0.04 μm² area, 0.25 clock-cycle latency, and markedly reduced quantum cost, representing a 34.29% cell reduction relative to strong recent baselines. Likewise, the CSA requires only 424 cells within 0.56 μm², delivering an 18.62% reduction in cell count against its best-known counterpart while sustaining 1.75 clock-cycle latency. Energy-dissipation analysis indicates low total/average energies (QCAFA: 1.31/1.10 eV; CSA: 3.66/3.50 eV), and temperature sweeps confirm stable output polarisation across 1–7 K, underscoring robustness under canonical QCA operating conditions. Comprehensive benchmarking against state-of-the-art single and multilayer designs verifies consistent gains in cell count, area utilisation, quantum cost, and delay. By uniting single-layer manufacturability with system-level efficiency, these adders advance QCA from component-level novelty toward practical nanoscale arithmetic fabrics, charting a credible pathway for energy-efficient, densely integrated post-CMOS computing.