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<p>The standard cell library has become an important component of today’s digital integrated circuit design. Since there are a large number of cells in the standard cell library, the layout design is a challenging task, especially for different processes with different design rules. In order to improve the development efficiency of the standard cell library and meet manufacturability requirements, an improved genetic algorithm is proposed for automatically generating standard cell layouts. It is demonstrated that the generated standard cell layout has higher quality with DRC (Design Rule Check) clean. Moreover, setting device information and design rules as adjustable variable parameters, this strategy can meet the migration of different design rules at different process nodes, which is proven that the proposed method can assist in the development of EDA tools for automatically generating standard cell layout.</p>

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A strategy for automatic generation of standard cell layout with the ability of migration to different process nodes

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2025年8月27日

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  • Wenli Haung,
  • Bin Li,
  • Wenchao Liu,
  • Zhaohui Wu,
  • Chaozheng Qin,
  • Lele Chen,
  • Yiming Huang

摘要

The standard cell library has become an important component of today’s digital integrated circuit design. Since there are a large number of cells in the standard cell library, the layout design is a challenging task, especially for different processes with different design rules. In order to improve the development efficiency of the standard cell library and meet manufacturability requirements, an improved genetic algorithm is proposed for automatically generating standard cell layouts. It is demonstrated that the generated standard cell layout has higher quality with DRC (Design Rule Check) clean. Moreover, setting device information and design rules as adjustable variable parameters, this strategy can meet the migration of different design rules at different process nodes, which is proven that the proposed method can assist in the development of EDA tools for automatically generating standard cell layout.