<p>The impedance characteristics of Power Distribution Networks (PDN) at the circuit level have always been critical in high-speed circuit design. However, to address power integrity issues caused by the reduction in chip feature sizes and the rapid increase in integrated circuit transistors counts, it is necessary to suppress power noise and meet the PDN impedance requirements of target device. This paper first analyzes the impedance characteristics of key device units, such as decoupling capacitors, and their PDN circuit models through modeling and simulation. It investigates optimization methods for anti-resonance spike and implements a multi-layer decoupling optimization strategy based on circuit parameters. Building on this, an impedance optimization strategy is proposed, combining coarse-grained computation based on target impedance parameters with fine-tuning to suppress anti-resonance spike. By leveraging the multi-stage cascading characteristics of decoupling capacitors and their typical parasitic parameters, circuit parameters and affected frequency ranges that meet the target impedance requirements are calculated. This allows for rapid determination of matching component data for each range. With additional circuit parasitic parameters considered, the strategy employs optimization methods to fine-tune the suppression of anti-resonance spike, thereby reducing PDN impedance across the entire frequency band during the design phase. This method is applied to a 5G small cell platform system, allowing for the quick determination of the parameters and quantities of circuit-matching components at the Printed Circuit Board (PCB) level. Compared to the original design, it significantly reduces component costs and capacitor installation area, thereby reducing PCB size.</p>