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<p>Low-power Decimation-in-Time Fast Fourier Transform (DIT FFT) architectures are crucial for energy-constrained applications like IoT and mobile computing. This work presents an efficient design methodology for 4-point Radix-2 DIT FFT architectures using both standard and hybrid approaches. The main contribution is the development of Minimal Gate Half Adder (MGHA) and Minimal Gate Full Adder (MGFA) designs. The optimized Carry Save Adders (CSAs) and Kogge-Stone Adders (KSAs) serve as the foundation for implementing Wallace multipliers (WMs) and Vedic multipliers (VMs). These multipliers are incorporated into 4-bit Standard Complex Multipliers (SCMs) and 4-bit Hybrid Complex Multipliers (HCMs) within the FFT architecture. The Standard 4-point Radix-2 DIT FFT (SFFT) uses conventional arithmetic blocks, while the Hybrid 4-point Radix-2 DIT FFT (HFFT) employs modular hybrid computation for enhanced efficiency. Both designs are implemented and simulated using Cadence Virtuoso with GPDK 180&#xa0;nm CMOS technology and further analyzed under Subthreshold Adiabatic Logic (SAL) to evaluate low-power performance. This methodology aims to achieve a balanced trade-off among power, delay, and area, demonstrating its suitability for resource-limited digital signal processing systems.</p>

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A novel low-power design of standard and hybrid 4-bit 4-point Radix-2 FFT architectures using CMOS and SAL with MGHA based arithmetic modules

  • 期刊论文

  • 发表日期：

    2025年10月25日

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  • Sagara Pandu,
  • J. Bhaskara Rao,
  • B. Nalini

摘要

Low-power Decimation-in-Time Fast Fourier Transform (DIT FFT) architectures are crucial for energy-constrained applications like IoT and mobile computing. This work presents an efficient design methodology for 4-point Radix-2 DIT FFT architectures using both standard and hybrid approaches. The main contribution is the development of Minimal Gate Half Adder (MGHA) and Minimal Gate Full Adder (MGFA) designs. The optimized Carry Save Adders (CSAs) and Kogge-Stone Adders (KSAs) serve as the foundation for implementing Wallace multipliers (WMs) and Vedic multipliers (VMs). These multipliers are incorporated into 4-bit Standard Complex Multipliers (SCMs) and 4-bit Hybrid Complex Multipliers (HCMs) within the FFT architecture. The Standard 4-point Radix-2 DIT FFT (SFFT) uses conventional arithmetic blocks, while the Hybrid 4-point Radix-2 DIT FFT (HFFT) employs modular hybrid computation for enhanced efficiency. Both designs are implemented and simulated using Cadence Virtuoso with GPDK 180 nm CMOS technology and further analyzed under Subthreshold Adiabatic Logic (SAL) to evaluate low-power performance. This methodology aims to achieve a balanced trade-off among power, delay, and area, demonstrating its suitability for resource-limited digital signal processing systems.