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<p>The significance of reversible operations in nanotechnology and quantum computation has grown in recent years. The efficient design of reversible quantum gates is crucial for building scalable and resource-optimized quantum circuits. This work presents an optimized version of an existing universal reversible gate, the Parity Preserving Multiplexer (PPM) gate, referred to as the Modified PPM (M-PPM) gate. The optimization employs template matching and commutation-based techniques to reduce gate count and circuit depth. The M-PPM gate achieves improvements of 16.6% in Controlled-NOT (CNOT) gates, 50% in Toffoli gates, 20% in total gate count, and 33.33% in circuit depth. It is further employed to construct a 4:1 quantum multiplexer, which shows respective improvements of 26.3%, 50%, 20%, and 29.1% in the same metrics. Both designs are decomposed into the NOT, CNOT, V, and V<sup>†</sup> (NCV) gate library to ensure fault-tolerant compatibility. These results confirm the efficiency and practical value of the proposed gate for quantum circuit design.</p>

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Template-based optimization of universal quantum reversible logic design for enhanced metrics

  • 期刊论文

  • 发表日期：

    2025年8月29日

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  • Mamtha Prajapati,
  • Kalyan Babu Killana

摘要

The significance of reversible operations in nanotechnology and quantum computation has grown in recent years. The efficient design of reversible quantum gates is crucial for building scalable and resource-optimized quantum circuits. This work presents an optimized version of an existing universal reversible gate, the Parity Preserving Multiplexer (PPM) gate, referred to as the Modified PPM (M-PPM) gate. The optimization employs template matching and commutation-based techniques to reduce gate count and circuit depth. The M-PPM gate achieves improvements of 16.6% in Controlled-NOT (CNOT) gates, 50% in Toffoli gates, 20% in total gate count, and 33.33% in circuit depth. It is further employed to construct a 4:1 quantum multiplexer, which shows respective improvements of 26.3%, 50%, 20%, and 29.1% in the same metrics. Both designs are decomposed into the NOT, CNOT, V, and V† (NCV) gate library to ensure fault-tolerant compatibility. These results confirm the efficiency and practical value of the proposed gate for quantum circuit design.