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<p>In space applications, cosmic radiation-induced multiple cells upset (MCU) poses a major stability issue for static random-access memory (SRAM). During the past decade, radiation-induced MCUs have been responsible for a significant increase in the proportion of mistakes affecting multiple memory cells. This research proposes an Interleave Multibit Parity Code (IMPC) for Octa multibit upset correction in SRAM, achieving low latency and error rates. The IMPC technique predicts MCUs before decoding and corrects adjacent 8-bit errors effectively, utilizing a parity-check matrix with minimal redundancy. Additionally, the encoder is reused to reduce overhead without interfering with the encoding and decoding process by reducing the area overhead of additional circuits. With the 45-nm library, encoders and decoders can be constructed with a minimal amount of area and delay overhead. Experimental results shows that the proposed code is more area-efficient, faster, and more power-efficient than current ECC codes.</p>

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Octa multibit upset correction in SRAM memories using interleaved MPC code

  • 期刊论文

  • 发表日期：

    2025年3月31日

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  • T. V. Sindhu,
  • P. Kalpana Devi

摘要

In space applications, cosmic radiation-induced multiple cells upset (MCU) poses a major stability issue for static random-access memory (SRAM). During the past decade, radiation-induced MCUs have been responsible for a significant increase in the proportion of mistakes affecting multiple memory cells. This research proposes an Interleave Multibit Parity Code (IMPC) for Octa multibit upset correction in SRAM, achieving low latency and error rates. The IMPC technique predicts MCUs before decoding and corrects adjacent 8-bit errors effectively, utilizing a parity-check matrix with minimal redundancy. Additionally, the encoder is reused to reduce overhead without interfering with the encoding and decoding process by reducing the area overhead of additional circuits. With the 45-nm library, encoders and decoders can be constructed with a minimal amount of area and delay overhead. Experimental results shows that the proposed code is more area-efficient, faster, and more power-efficient than current ECC codes.