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<p>Due to cost benefits, supply chains of integrated circuits (ICs) are largely outsourced nowadays. However, passing ICs through various third-party providers gives rise to many security threats, like piracy of IC intellectual property or insertion of hardware Trojans, i.e., malicious circuit modifications. In this work, we proactively and systematically protect the physical layouts of ICs against post-design insertion of Trojans. Toward that end, we propose <i>TroLLoc</i>, a novel scheme for IC security closure that employs, in careful unison, logic locking and layout hardening, i.e., physical synthesis aimed toward highest possible utilization. <i>TroLLoc</i> is fully integrated into a commercial-grade design flow, and shown to be effective, efficient, and robust. Our work provides in-depth layout and security analysis considering the ISPD’22/23 benchmarks for security closure <i>TroLLoc</i> successfully renders layouts resilient, with reasonable overheads, against (i)&#xa0;general prospects for Trojan insertion as in the ISPD’22 contest, (ii)&#xa0;actual Trojan insertion as in the ISPD’23 contest, and (iii)&#xa0;second-order attacks where adversaries would first (before Trojan insertion) try to bypass the locking defense, mainly using advanced machine learning attacks. Finally, we release all our artifacts for independent verification&#xa0;[<CitationRef CitationID="CR64">64</CitationRef>].</p>

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TroLLoc: Security Closure against Hardware Trojans by Logic Locking and Layout Hardening

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年4月1日

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  • Fangzhou Wang,
  • Qijing Wang,
  • Lilas Alrahis,
  • Bangqi Fu,
  • Shui Jiang,
  • Xiaopeng Zhang,
  • Ozgur Sinanoglu,
  • Tsung-Yi Ho,
  • Evangeline F. Y. Young,
  • Johann Knechtel

摘要

Due to cost benefits, supply chains of integrated circuits (ICs) are largely outsourced nowadays. However, passing ICs through various third-party providers gives rise to many security threats, like piracy of IC intellectual property or insertion of hardware Trojans, i.e., malicious circuit modifications. In this work, we proactively and systematically protect the physical layouts of ICs against post-design insertion of Trojans. Toward that end, we propose TroLLoc, a novel scheme for IC security closure that employs, in careful unison, logic locking and layout hardening, i.e., physical synthesis aimed toward highest possible utilization. TroLLoc is fully integrated into a commercial-grade design flow, and shown to be effective, efficient, and robust. Our work provides in-depth layout and security analysis considering the ISPD’22/23 benchmarks for security closure TroLLoc successfully renders layouts resilient, with reasonable overheads, against (i) general prospects for Trojan insertion as in the ISPD’22 contest, (ii) actual Trojan insertion as in the ISPD’23 contest, and (iii) second-order attacks where adversaries would first (before Trojan insertion) try to bypass the locking defense, mainly using advanced machine learning attacks. Finally, we release all our artifacts for independent verification [64].