This paper describes the design and implementation of a Fredkin-gate (FRG)-based arbiter physically unclonable function (PUF) with 2 \(\times\) 2 switch blocks on an Artix-7 FPGA. The Fredkin gate is a three-input, three-output reversible gate, with two of its outputs functioning as 2:1 multiplexers. A classical arbiter PUF consists of multiplexer-based switch blocks through which a trigger signal propagates; therefore we propose a Fredkin-gate-based arbiter PUF architecture. The designed arbiter PUF is manually placed and routed on the Artix-7 200T FPGA. Challenges were generated using an LFSR, and the corresponding responses were analyzed to compute standard PUF performance metrics. The uniformity and uniqueness of the Fredkin gate-based arbiter PUF are 48.62% and 48.11%, respectively. Compared with a conventional irreversible gate-based arbiter PUF, the proposed design shows an improvement of 12.49% in uniformity and 3.24% in uniqueness. The reliability, BER, and KER of the proposed Fredkin gate-based arbiter PUF are 91.9%, 8.1%, and 0.9827, respectively. The proposed design was also evaluated under ML-based modeling attacks and demonstrates improved resistance compared with the conventional arbiter PUF.
