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<p>The fast evolution of resource-constrained Internet of Things (IoT) devices necessitates lightweight cryptographic solutions that balance robust security with minimal hardware demands. This paper presents a comprehensive benchmarking study of FPGA-based implementations of the SIMON 64/128 block cipher, a lightweight algorithm designed by the NSA for efficient hardware realization. Three architectural strategies are evaluated on an Artix-7 FPGA: an iterative design with a precomputed key schedule (Iter-PreK), an iterative design with an on-the-fly key schedule (Iter-OTFK), and a partially unrolled design (Unrollx2) processing two rounds per clock cycle. Experimental results reveal distinct trade-offs in resource utilization, latency, throughput, and power consumption. The Iter-OTFK design offers the smallest footprint, occupying only 82 slices and consuming 79&#xa0;mW, while still achieving a throughput of 267.0&#xa0;Mbps by overlapping encryption and key scheduling. Iter-PreK provides a balanced design, reaching 211.1&#xa0;Mbps at a maximum frequency of 151.7&#xa0;MHz with a moderate area. In contrast, the partially unrolled Unrollx2 architecture achieves a peak steady-state throughput of 5014.4&#xa0;Mbps at 156.7&#xa0;MHz, with significantly improved energy efficiency (0.017&#xa0;nJ/bit), making it ideal for bandwidth-intensive applications. Compared to prior studies, this work presents the first systematic benchmarking of SIMON 64/128 across multiple architectures on a modern FPGA, offering practical design guidelines for lightweight cryptography in IoT deployments, from low-end sensor nodes to high-throughput gateways.</p>

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Benchmarking Design Trade-offs in FPGA Implementations of SIMON 64/128 Cipher

  • 期刊论文

  • 发表日期：

    2025年9月20日

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  • W. A. Susantha Wijesinghe

摘要

The fast evolution of resource-constrained Internet of Things (IoT) devices necessitates lightweight cryptographic solutions that balance robust security with minimal hardware demands. This paper presents a comprehensive benchmarking study of FPGA-based implementations of the SIMON 64/128 block cipher, a lightweight algorithm designed by the NSA for efficient hardware realization. Three architectural strategies are evaluated on an Artix-7 FPGA: an iterative design with a precomputed key schedule (Iter-PreK), an iterative design with an on-the-fly key schedule (Iter-OTFK), and a partially unrolled design (Unrollx2) processing two rounds per clock cycle. Experimental results reveal distinct trade-offs in resource utilization, latency, throughput, and power consumption. The Iter-OTFK design offers the smallest footprint, occupying only 82 slices and consuming 79 mW, while still achieving a throughput of 267.0 Mbps by overlapping encryption and key scheduling. Iter-PreK provides a balanced design, reaching 211.1 Mbps at a maximum frequency of 151.7 MHz with a moderate area. In contrast, the partially unrolled Unrollx2 architecture achieves a peak steady-state throughput of 5014.4 Mbps at 156.7 MHz, with significantly improved energy efficiency (0.017 nJ/bit), making it ideal for bandwidth-intensive applications. Compared to prior studies, this work presents the first systematic benchmarking of SIMON 64/128 across multiple architectures on a modern FPGA, offering practical design guidelines for lightweight cryptography in IoT deployments, from low-end sensor nodes to high-throughput gateways.