<p>Due to the perils posed by side-channel attacks and the critical limitations of existing post-silicon assessment solutions, such as low flexibility and extensive expertise requirements, the demand for pre-silicon side-channel security verification has increased significantly. In this paper, we present a novel approach for electromagnetic (EM) side-channel leakage assessment at the gate-level abstraction. More specifically, our framework builds a design-agnostic EM leakage model by focusing on switching activities of registers, the main contributor to in-field EM side-channel emissions, and register fanouts to provide a high-confidence indication of design leakiness. Additionally, empirical layout-level data is back-annotated to the EM model for simulating gate-level estimated EM traces and calculate security metrics to quantify design-level leakage. Our approach ensures the utmost flexibility in deploying countermeasures since it evaluates side-channel leakage behavior accurately at an early design stage. More importantly, designs with information leakage can be detected in early stage, significantly reducing the secure design time and the need for iterative layout-level simulations. To demonstrate the effectiveness of our approach, we conduct extensive experiments on AES benchmarks, showing that the designs identified as leaky at the gate-level consistently exhibit leakiness in post-silicon assessments (FPGA prototyping). This highlights the potential of our approach for early stage security evaluation and the reduction of design iterations required for achieving robust EM side-channel resistance.</p>