Purpose <p>Radio frequency (RF) power sources are critical yet vulnerable components in linear accelerators. Fast-responding faults such as arcing can cause catastrophic damage to expensive klystrons and accelerating structures. The purpose of this study was to design, develop, and implement a dedicated fast interlock system for the RF power sources of the China Spallation Neutron Source (CSNS) linac, aiming to achieve microsecond-level response for enhanced equipment protection.</p> Methods <p>We developed a novel system based on a Field-Programmable Gate Array (FPGA) platform, replacing traditional analog circuits or Programmable Logic Controllers (PLCs). The system core utilized an Altera Cyclone III FPGA to continuously monitor fault signals from the RF stations, including reflected power (indicating VSWR), arc detector signals, and output power. Upon detection of any predefined fault condition, the FPGA logic would generate a shutdown signal to cut off the RF excitation within microseconds. The hardware architecture, signal sampling methodology, and protection logic were detailed.</p> Results <p>The developed fast interlock system successfully achieved a response time of less than 2 microseconds from fault detection to RF shutdown. It has been fully integrated into the CSNS linac’s RF control system. Since its commissioning in 2018, the system has been in stable and reliable operation for over seven years, effectively protecting the klystrons and accelerating cavities from damage during fault events</p> Conclusions <p>This study demonstrates the successful development and long-term application of an FPGA-based fast interlock system for high-power RF sources. The system fulfills the critical requirement for microsecond-level protection, offering superior speed, flexibility, and reliability compared to conventional solutions, and provides a robust safeguard for the stable operation of the CSNS accelerator.</p>