This paper explores the impact of back-gate bias ( \(V_\text {soi}\) ) and supply voltage ( \(V_\text {DD}\) ) on the single-event upset (SEU) cross section of 0.18 µm configurable silicon-on-insulator static random-access memory (SRAM) under high linear energy transfer heavy-ion experimentation. The experimental findings demonstrate that applying a negative back-gate bias to NMOS and a positive back-gate bias to PMOS enhances the SEU resistance of SRAM. Specifically, as the back-gate bias for N-type transistors ( \(V_\text {nsoi}\) ) decreases from 0 to −10 V, the SEU cross section decreases by 93.23%, whereas an increase in the back-gate bias for P-type transistors ( \(V_\text {psoi}\) ) from 0 to 10 V correlates with an 83.7% reduction in SEU cross section. Furthermore, a significant increase in the SEU cross section was observed with increase in supply voltage, as evidenced by a 159% surge at \(V_\text {DD}\) = 1.98 V compared with the nominal voltage of 1.8 V. To explore the physical mechanisms underlying these experimental data, we analyzed the dependence of the critical charge of the circuit and the collected charge on the bias voltage by simulating SEUs using technology computer-aided design.
