<p>This study presents a low-noise, high-rate front-end readout application-specific integrated circuit (ASIC) designed for the electromagnetic calorimeter (ECAL) of the Super Tau-Charm Facility (STCF). To address the high background-count rate in the STCF ECAL, the temporal features of signals are analyzed node-by-node along the chain of the analog front-end circuit. Then, the system is optimized to mitigate the pile-up effects and elevate the count rate to megahertz levels. First, a charge-sensitive amplifier (CSA) with a fast reset path is developed, enabling quick resetting when the output reaches the maximum amplitude. This prevents the CSA from entering a pulse-dead zone owing to amplifier saturation caused by the pile-up. Second, a high-order shaper with baseline holder circuits is improved to enhance the anti-pile-up capability while maintaining an effective noise-filtering performance. Third, a high-speed peak-detection and hold circuit with an asynchronous first-input-first-output buffer function is proposed to hold and read the piled-up signals of the shaper. The ASIC is designed and manufactured using a standard commercial 1P6M <InlineEquation ID="IEq1"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="41365_2025_1640_Article_IEq1.gif" Format="GIF" Height="16" Rendition="HTML" Resolution="72" Type="Linedraw" Width="57" /> </InlineMediaObject> <EquationSource Format="TEX">${0.18}\,{\upmu }\hbox {m}$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mrow> <mn>0.18</mn> </mrow> <mspace width="0.166667em" /> <mi mathvariant="normal">μ</mi> <mtext>m</mtext> </mrow> </math></EquationSource> </InlineEquation> mixed-signal CMOS process with a chip area of <InlineEquation ID="IEq2"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="41365_2025_1640_Article_IEq2.gif" Format="GIF" Height="14" Rendition="HTML" Resolution="72" Type="Linedraw" Width="123" /> </InlineMediaObject> <EquationSource Format="TEX">${2.4}\,\hbox {mm} \times {1.6}\,\hbox {mm}$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mrow> <mn>2.4</mn> </mrow> <mspace width="0.166667em" /> <mtext>mm</mtext> <mo>×</mo> <mrow> <mn>1.6</mn> </mrow> <mspace width="0.166667em" /> <mtext>mm</mtext> </mrow> </math></EquationSource> </InlineEquation>. The measurement results demonstrate a dynamic range of 4–500 fC with a nonlinearity error below 1.5<InlineEquation ID="IEq3"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="41365_2025_1640_Article_IEq3.gif" Format="GIF" Height="16" Rendition="HTML" Resolution="72" Type="Linedraw" Width="15" /> </InlineMediaObject> <EquationSource Format="TEX">$\%$</EquationSource> <EquationSource Format="MATHML"><math> <mo>%</mo> </math></EquationSource> </InlineEquation>. For periodically distributed input signals, a count rate of 1.5 MHz/Ch is achieved with a peak time of 360 ns, resulting in an equivalent noise charge (ENC) of <InlineEquation ID="IEq4"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="41365_2025_1640_Article_IEq4.gif" Format="GIF" Height="16" Rendition="HTML" Resolution="72" Type="Linedraw" Width="54" /> </InlineMediaObject> <EquationSource Format="TEX">${2500}\,\hbox {e}^{-}$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>2500</mn> <mspace width="0.166667em" /> <msup> <mtext>e</mtext> <mo>-</mo> </msup> </mrow> </math></EquationSource> </InlineEquation>. The maximum count rate is 4 MHz/Ch at a peak time of 120 ns. At a peak time of <InlineEquation ID="IEq5"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="41365_2025_1640_Article_IEq5.gif" Format="GIF" Height="16" Rendition="HTML" Resolution="72" Type="Linedraw" Width="50" /> </InlineMediaObject> <EquationSource Format="TEX">${1.68}\,{\upmu }\hbox {s}$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mrow> <mn>1.68</mn> </mrow> <mspace width="0.166667em" /> <mi mathvariant="normal">μ</mi> <mtext>s</mtext> </mrow> </math></EquationSource> </InlineEquation> with a 270 pF external capacitance, the minimum ENC is <InlineEquation ID="IEq6"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="41365_2025_1640_Article_IEq6.gif" Format="GIF" Height="16" Rendition="HTML" Resolution="72" Type="Linedraw" Width="54" /> </InlineMediaObject> <EquationSource Format="TEX">${1966}\,\hbox {e}^{-}$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>1966</mn> <mspace width="0.166667em" /> <msup> <mtext>e</mtext> <mo>-</mo> </msup> </mrow> </math></EquationSource> </InlineEquation>, and the noise slope is <InlineEquation ID="IEq7"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="41365_2025_1640_Article_IEq7.gif" Format="GIF" Height="19" Rendition="HTML" Resolution="72" Type="Linedraw" Width="78" /> </InlineMediaObject> <EquationSource Format="TEX">${3.08}\,\hbox {e}^{-}/\hbox {pF}$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mrow> <mn>3.08</mn> </mrow> <mspace width="0.166667em" /> <msup> <mtext>e</mtext> <mo>-</mo> </msup> <mo stretchy="false">/</mo> <mtext>pF</mtext> </mrow> </math></EquationSource> </InlineEquation>. The timing resolution is better than 125 ps at an input charge of 200 fC. The power consumption is 35 mW/Ch.</p>

Low-noise and high-rate front-end ASIC for APD detectors in STCF ECAL

期刊论文
发表日期：

2025年3月8日

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Chao Liu,
Ran Zheng,
Jia Wang,
Xiao-Min Wei,
Fei-Fei Xue,
Rui-Guang Zhao,
Yann Hu

摘要

This study presents a low-noise, high-rate front-end readout application-specific integrated circuit (ASIC) designed for the electromagnetic calorimeter (ECAL) of the Super Tau-Charm Facility (STCF). To address the high background-count rate in the STCF ECAL, the temporal features of signals are analyzed node-by-node along the chain of the analog front-end circuit. Then, the system is optimized to mitigate the pile-up effects and elevate the count rate to megahertz levels. First, a charge-sensitive amplifier (CSA) with a fast reset path is developed, enabling quick resetting when the output reaches the maximum amplitude. This prevents the CSA from entering a pulse-dead zone owing to amplifier saturation caused by the pile-up. Second, a high-order shaper with baseline holder circuits is improved to enhance the anti-pile-up capability while maintaining an effective noise-filtering performance. Third, a high-speed peak-detection and hold circuit with an asynchronous first-input-first-output buffer function is proposed to hold and read the piled-up signals of the shaper. The ASIC is designed and manufactured using a standard commercial 1P6M ${0.18}\,{\upmu }\hbox {m}$ $0.18 μ m$ mixed-signal CMOS process with a chip area of ${2.4}\,\hbox {mm} \times {1.6}\,\hbox {mm}$ $2.4 mm \times 1.6 mm$ . The measurement results demonstrate a dynamic range of 4–500 fC with a nonlinearity error below 1.5 $\%$ $%$ . For periodically distributed input signals, a count rate of 1.5 MHz/Ch is achieved with a peak time of 360 ns, resulting in an equivalent noise charge (ENC) of ${2500}\,\hbox {e}^{-}$ $2500 e^{-}$ . The maximum count rate is 4 MHz/Ch at a peak time of 120 ns. At a peak time of ${1.68}\,{\upmu }\hbox {s}$ $1.68 μ s$ with a 270 pF external capacitance, the minimum ENC is ${1966}\,\hbox {e}^{-}$ $1966 e^{-}$ , and the noise slope is ${3.08}\,\hbox {e}^{-}/\hbox {pF}$ $3.08 e^{-} / pF$ . The timing resolution is better than 125 ps at an input charge of 200 fC. The power consumption is 35 mW/Ch.