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<p>The increasing need for low-power and compact analog circuitry has highlighted the limitations of traditional phase-shift oscillators that depend on operational amplifiers, which typically incur higher power consumption and larger silicon area. To address these challenges, this work introduces a CNTFET-based quadrature oscillator that removes OPAMPs within the proposed topology and employs a simplified differentiator–inverter architecture. This approach reduces power consumption and layout complexity while maintaining stable sinusoidal and quadrature operation. Simulations based on the Stanford CNTFET model demonstrate that the proposed oscillator achieves a maximum oscillation frequency of 460&#xa0;MHz. Detailed transient, spectral, and phase-noise analyses are presented at a representative operating point around 96&#xa0;MHz, where stable quadrature operation is observed with a total power consumption of 256 µW .The circuit maintains predictable behavior across process, voltage, and temperature (PVT) variations, and its minimal reliance on passive components further enhances area efficiency. Owing to its simplicity and robustness, the proposed oscillator is well suited for low-power analog and mixed-signal subsystems that require compact design and reliable MHz-range sinusoidal generation. These findings establish a practical foundation for future CNTFET-based or hybrid mixed-technology building blocks aimed at energy-efficient integrated circuit design.</p>

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An Op-Amp-Less CNTFET-Based Sinusoidal Quadrature Oscillator Using Cascaded Differentiator Stages

  • 期刊论文

  • 发表日期：

    2026年7月7日

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  • Ahmad Karimi

摘要

The increasing need for low-power and compact analog circuitry has highlighted the limitations of traditional phase-shift oscillators that depend on operational amplifiers, which typically incur higher power consumption and larger silicon area. To address these challenges, this work introduces a CNTFET-based quadrature oscillator that removes OPAMPs within the proposed topology and employs a simplified differentiator–inverter architecture. This approach reduces power consumption and layout complexity while maintaining stable sinusoidal and quadrature operation. Simulations based on the Stanford CNTFET model demonstrate that the proposed oscillator achieves a maximum oscillation frequency of 460 MHz. Detailed transient, spectral, and phase-noise analyses are presented at a representative operating point around 96 MHz, where stable quadrature operation is observed with a total power consumption of 256 µW .The circuit maintains predictable behavior across process, voltage, and temperature (PVT) variations, and its minimal reliance on passive components further enhances area efficiency. Owing to its simplicity and robustness, the proposed oscillator is well suited for low-power analog and mixed-signal subsystems that require compact design and reliable MHz-range sinusoidal generation. These findings establish a practical foundation for future CNTFET-based or hybrid mixed-technology building blocks aimed at energy-efficient integrated circuit design.