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<p>Low power successive approximation register analogue to digital converters (SAR ADC) are essential and important blocks in many applications, such as IoT sensors, microcontrollers, implantable ICs, etc. In the past, a high percentage of power consumption of this converter was related to the capacitor network section, but now, with new topologies and the gradual reduction of capacitor network, the shift register and shift code register blocks are the primary consumers of power. This paper proposes a new SAR-ADC state machine that uses FFs without SET and RESET pins. With the innovative approach, little extra logic gate is required compared with previous state machines. With the SET and RESET requirement of the flip-flops removed, a low power 8 transistor dynamic flip-flop is designed for the corresponding state machine. The proposed dynamic flip flop is characterized and shown to meet the requirements of the state machine. The suggested approach can be employed in SAR ADC designs suffering from high power dissipation percentage in their digital section. Based on the simulation results, in the worst case, the power of the digital section and the whole converter can be improved by more than 60% and 16%, respectively (in the monotonic switching scheme).</p>

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A New Energy-Efficient Dynamic State Machine for SAR ADCs

  • 期刊论文

  • 发表日期：

    2026年4月18日

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  • Mehdi Sotoudeh,
  • Mehdi Habibi

摘要

Low power successive approximation register analogue to digital converters (SAR ADC) are essential and important blocks in many applications, such as IoT sensors, microcontrollers, implantable ICs, etc. In the past, a high percentage of power consumption of this converter was related to the capacitor network section, but now, with new topologies and the gradual reduction of capacitor network, the shift register and shift code register blocks are the primary consumers of power. This paper proposes a new SAR-ADC state machine that uses FFs without SET and RESET pins. With the innovative approach, little extra logic gate is required compared with previous state machines. With the SET and RESET requirement of the flip-flops removed, a low power 8 transistor dynamic flip-flop is designed for the corresponding state machine. The proposed dynamic flip flop is characterized and shown to meet the requirements of the state machine. The suggested approach can be employed in SAR ADC designs suffering from high power dissipation percentage in their digital section. Based on the simulation results, in the worst case, the power of the digital section and the whole converter can be improved by more than 60% and 16%, respectively (in the monotonic switching scheme).