<p>The current mainstream in integrated circuits is the copper (Cu) metal process; therefore, the interconnects are made of Cu to reduce propagation delays and power consumption. However, due to its high diffusion coefficient, Cu wires tend to form deep energy levels in silicon substrates, leading to degradation in device performance. Additionally, poor adhesion of Cu to dielectric layers severely affects device efficiency. Therefore, research on metallization diffusion barrier layers is needed to overcome the inherent drawbacks of Cu wires. Hence, in semiconductor Cu processes, physical vapor deposition (PVD) of tantalum/tantalum nitride (Ta/TaN) multilayers are of crucial importance, serving as a liner/barrier layer in PVD to prevent diffusion between Cu and silicon (Si) substrates. This study aims to increase the life span of PVD chamber kits, reduce particle shedding, and improve process quality. It has practical implications for the semiconductor industry. In practice, wire-arc spray directed energy deposition (DED) layers inside the chamber induce surface roughness, enhancing the adhesion of Ta/TaN films. However, peeling occurs when the PVD film reaches a specific thickness, generating particles. Therefore, this study utilizes finite element analysis (FEA) to examine the Ta/TaN multilayer stress distribution. Simulation results indicate that the leading cause of film peeling is the presence of sharp points on the coating layer surface, which act as points of current density concentration. Consequently, this manuscript's main contribution is that electrochemical polishing (ECP) is initially proposed and employed, and optimal electrochemical parameters are determined through simulation to preferentially remove these sharp points, improving the curvature of the coating surface. This subsequently reduces stress concentration in the Ta/TaN film, enhances process quality, and is experimentally validated by reducing the probability of out-of-control (OOC) occurrences from 12.5% to 2.5%.</p>