Scholarlink

<p>Efficient real-time data processing in modern AI and IoT devices requires ultra-low-power consumption and minimal latency. Flip-flops (FFs), being fundamental sequential elements, play a crucial role in determining system performance and energy efficiency. This work presents a novel Negative-Edge Triggered True Single-Phase Clocked Flip-Flop (NET-TSPC-FF) implemented using a 7&#xa0;nm FinFET process. The proposed design is evaluated across a wide temperature range to investigate the impact of the Temperature Inversion Effect (TIE), a phenomenon in advanced FinFET technologies where delay and power exhibit a reverse trend compared to conventional CMOS devices. Simulation results demonstrate that the FinFET-based NET-TSPC-FF achieves significantly lower latency of 12.72&#xa0;ps using 7&#xa0;nm FinFET process compared to 27.95&#xa0;ps using 22&#xa0;nm CMOS at 300&#xa0;K and reduced power consumption of 0.86&#xa0;μW using 7&#xa0;nm FinFET process compared to 5.19&#xa0;μW using 22&#xa0;nm CMOS. Furthermore, under higher temperatures (380&#xa0;K), latency in FinFET-based FFs continues to improve while CMOS counterparts degrade, highlighting the influence of TIE. Overall, the proposed design demonstrates superior performance, validating its suitability for ultra-low-power, high-speed AI, and IoT applications.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Thermal dynamics of 7-nm FinFET process-based negative edge triggered (NET) TSPC D flip-flop for future AI and IoT applications

  • 期刊论文

  • 发表日期：

    2025年10月22日

查看全文
  • Syeda Hurmath Juveria,
  • R. Shashank,
  • Asisa Kumar Panigrahy,
  • J. Ajayan

摘要

Efficient real-time data processing in modern AI and IoT devices requires ultra-low-power consumption and minimal latency. Flip-flops (FFs), being fundamental sequential elements, play a crucial role in determining system performance and energy efficiency. This work presents a novel Negative-Edge Triggered True Single-Phase Clocked Flip-Flop (NET-TSPC-FF) implemented using a 7 nm FinFET process. The proposed design is evaluated across a wide temperature range to investigate the impact of the Temperature Inversion Effect (TIE), a phenomenon in advanced FinFET technologies where delay and power exhibit a reverse trend compared to conventional CMOS devices. Simulation results demonstrate that the FinFET-based NET-TSPC-FF achieves significantly lower latency of 12.72 ps using 7 nm FinFET process compared to 27.95 ps using 22 nm CMOS at 300 K and reduced power consumption of 0.86 μW using 7 nm FinFET process compared to 5.19 μW using 22 nm CMOS. Furthermore, under higher temperatures (380 K), latency in FinFET-based FFs continues to improve while CMOS counterparts degrade, highlighting the influence of TIE. Overall, the proposed design demonstrates superior performance, validating its suitability for ultra-low-power, high-speed AI, and IoT applications.