<p>Recent research in low-power device development focused their goal on shifting the architecture of field-effect transistors (FET) from Boltzmann FET to tunnel FET (TFET) and Landau FET. This paper delves into the optimization and simulation of a novel source-modified ferroelectric-TFET (SM-Fe-TFET) device, exploring its electrical characteristics, performance metrics, and design considerations. The introduction of a ferroelectric layer into the gate-oxide stack with capacitance matching leads to negative capacitance and results in internal voltage amplification and steep subthreshold characteristics. The proposed design utilizes the benefits of negative capacitance by integrating ferroelectric material in the gate stack, which helps to obtain a subthreshold swing of 27.541&#xa0;mV/decade, thus overcoming the Boltzmann tyranny. In addition, the structure utilizes the III/V GaSb material on the source side which reduces the tunneling barrier and enhances the mobility; hence the ON current is improved. The ON current of the device is improved to 10⁻³A/μm, and the OFF current is reduced to 10⁻¹⁴A/μm. The performance of the device has been analyzed across various temperatures, considering the temperature-dependent nature of the ferroelectric material, which undergoes phase transitions beyond a certain temperature. Further, the analysis of analog/RF and linearity parameters has been performed in the presence and absence of uniform trap charges which shows that trap charges degrade the performance of the device. The obtained maximum transconductance (<i>g</i>_m), cut-off frequency (<i>f</i>_c), Transconductance Frequency Product (TFP), and Gain Bandwidth Product of the proposed device in the absence of trap charges are 7.48 × 10^–4 A/V-µm, 1.08&#xa0;GHz, 28.6&#xa0;GHz/V, and 1.12&#xa0;GHz, respectively. These significant advancements make the proposed device a leading contender for future low-power and high-speed applications.</p>