Scholarlink

<p>Shift registers are basic sequential circuits used to store and transfer data in digital systems. This study presents the design, implementation, and performance of shift register architectures supported by Improved Diode-Free Adiabatic Logic (CNTFET-IDFAL) based on CNTFET-based clock-gated pair-shared flip-flops (multi-threshold CPSFFs). The proposed method combines the multi-threshold assignment of device assignment and adiabatic charge-recovery operation to minimize the switching loss, leakage power, and high-speed operation. To reduce unnecessary switching activity and enhance energy efficiency, the CPSFF architecture utilizes shared clocked pairs of transistors with discharge paths controlled by feedback. The size of the devices is determined with respect to the CNT structural parameters, and complementary split-level power clocks allow the devices to be charged and discharged at the internal nodes. The suggested design methodology was implemented in SISO, SIPO, PISO, and PIPO shift register designs and tested at 180 and 45&#xa0;nm technology nodes under the same operating conditions. The performance was evaluated in terms of power dissipation, propagation delay power-delay product, and transistor count. The simulation results revealed low power consumption, high energy efficiency, and competitive frequency operation compared with traditional implementations, confirming the usability of the proposed CNTFET-IDFAL CPSFF-based shift register architecture in the design of low-power digital circuits.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Design and Performance Analysis of CNTFET-Based Improved Diode-Free Adiabatic Logic Shift Registers Using Multi-Threshold Clocked Pair Shared Flip-Flop Architecture

  • 期刊论文

  • 发表日期：

    2026年6月16日

查看全文
  • K. Kalaichelvi,
  • M. Sundaram

摘要

Shift registers are basic sequential circuits used to store and transfer data in digital systems. This study presents the design, implementation, and performance of shift register architectures supported by Improved Diode-Free Adiabatic Logic (CNTFET-IDFAL) based on CNTFET-based clock-gated pair-shared flip-flops (multi-threshold CPSFFs). The proposed method combines the multi-threshold assignment of device assignment and adiabatic charge-recovery operation to minimize the switching loss, leakage power, and high-speed operation. To reduce unnecessary switching activity and enhance energy efficiency, the CPSFF architecture utilizes shared clocked pairs of transistors with discharge paths controlled by feedback. The size of the devices is determined with respect to the CNT structural parameters, and complementary split-level power clocks allow the devices to be charged and discharged at the internal nodes. The suggested design methodology was implemented in SISO, SIPO, PISO, and PIPO shift register designs and tested at 180 and 45 nm technology nodes under the same operating conditions. The performance was evaluated in terms of power dissipation, propagation delay power-delay product, and transistor count. The simulation results revealed low power consumption, high energy efficiency, and competitive frequency operation compared with traditional implementations, confirming the usability of the proposed CNTFET-IDFAL CPSFF-based shift register architecture in the design of low-power digital circuits.