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<p>An artificial neural network (ANN) is a type of computing system that models individual neural connections to imitate the information processing capabilities of the human brain. ANNs are used for solving complex problems in text data and tabular data. Convolutional neural networks (CNNs) are the most effective tools for resolving issues that are associated with computer vision and recurrent neural networks are applied for sequence data and natural language processing tools. The hardware chip design is always challenging to solve real-time problems. The research letter examines the comparative evaluation of the performance suitability of hardware chip designs for scalable computation, as well as the application of field programmable gate arrays in chip logic verification, utilizing parallel computing and pipelined design principles to enhance execution efficiency. CNN chip has demonstrated the optimal delay of 8.750&#xa0;ns, 2.510&#xa0;ns minimum time, and 552.00&#xa0;MHz frequency, 98.78% accuracy in comparison to ANN and RNN for scalable design of 64 neurons processing. The current demand within the artificial intelligence industry for wearable embedded system design necessitates the utilization of dedicated real-time hardware and customized design solutions.</p>

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Comparative Study of ANN, CNN, and RNN Hardware Chips

  • 期刊论文

  • 发表日期：

    2025年5月26日

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  • Akash Goel,
  • Alok Katiyar,
  • Amit Kumar Goel,
  • Adesh Kumar

摘要

An artificial neural network (ANN) is a type of computing system that models individual neural connections to imitate the information processing capabilities of the human brain. ANNs are used for solving complex problems in text data and tabular data. Convolutional neural networks (CNNs) are the most effective tools for resolving issues that are associated with computer vision and recurrent neural networks are applied for sequence data and natural language processing tools. The hardware chip design is always challenging to solve real-time problems. The research letter examines the comparative evaluation of the performance suitability of hardware chip designs for scalable computation, as well as the application of field programmable gate arrays in chip logic verification, utilizing parallel computing and pipelined design principles to enhance execution efficiency. CNN chip has demonstrated the optimal delay of 8.750 ns, 2.510 ns minimum time, and 552.00 MHz frequency, 98.78% accuracy in comparison to ANN and RNN for scalable design of 64 neurons processing. The current demand within the artificial intelligence industry for wearable embedded system design necessitates the utilization of dedicated real-time hardware and customized design solutions.