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<p>Physical Unclonable Functions (PUFs) are emerging security primitives designed to enhance the security of physical devices and overcome the challenges posed by conventional cryptographic algorithms. PUFs utilize logical operations to create a unique identity for each device based on the processing hardware’s unpredictable and non-reproducible physical characteristics. This generated key serves as device fingerprint providing a high level of security against cloning and counterfeiting. The dependence of PUFs on logical operation comes at the cost of exploiting the underlying hardware and contributes to the power consumption as well. This work addresses to reduce the resource consumption of delay-based Arbiter PUF(APUF) with help of Reversible Logic (RL) and its novel PUF design. RL is a computational method where each output state precisely determines its input, thereby reducing information loss and energy dissipation. This paper proposes a novel RL-based APUF design that generates 8/16/32 and 64-bit keys. The key generated is sensitive to the user input but not controlled by the user to maintain randomness. The research on PUFs shows that the best values of uniqueness, uniformity, and entropy metrics achieved across 8-bit/16-bit/32-bit and 64-bit implementations at 100%, 51% and 99.3%. The reliability obtained is 92.21% making the propose design a stable and robust model. Results have been evaluated using 28&#xa0;nm, Xilinx XC7a35tcp236-1 Basys3 board. The security analysis against Machine Learning (ML attacks-SVM, LR and ANN are significant with best prediction accuracy of 49.7% for SVM, 50.01% for LR and 50.02 for ANN. The results also establish efficient design with reduced power consumption of 3.52&#xa0;W for 64-bit response generation when compared with existing state of the art PUF designs.</p>

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Design and analysis of efficient homogenous arbiter physical unclonable function using reversible logic

  • 期刊论文

  • 发表日期：

    2026年7月2日

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  • Bhaskar Dutta,
  • Nishant Bansal,
  • Gaganpreet Kaur

摘要

Physical Unclonable Functions (PUFs) are emerging security primitives designed to enhance the security of physical devices and overcome the challenges posed by conventional cryptographic algorithms. PUFs utilize logical operations to create a unique identity for each device based on the processing hardware’s unpredictable and non-reproducible physical characteristics. This generated key serves as device fingerprint providing a high level of security against cloning and counterfeiting. The dependence of PUFs on logical operation comes at the cost of exploiting the underlying hardware and contributes to the power consumption as well. This work addresses to reduce the resource consumption of delay-based Arbiter PUF(APUF) with help of Reversible Logic (RL) and its novel PUF design. RL is a computational method where each output state precisely determines its input, thereby reducing information loss and energy dissipation. This paper proposes a novel RL-based APUF design that generates 8/16/32 and 64-bit keys. The key generated is sensitive to the user input but not controlled by the user to maintain randomness. The research on PUFs shows that the best values of uniqueness, uniformity, and entropy metrics achieved across 8-bit/16-bit/32-bit and 64-bit implementations at 100%, 51% and 99.3%. The reliability obtained is 92.21% making the propose design a stable and robust model. Results have been evaluated using 28 nm, Xilinx XC7a35tcp236-1 Basys3 board. The security analysis against Machine Learning (ML attacks-SVM, LR and ANN are significant with best prediction accuracy of 49.7% for SVM, 50.01% for LR and 50.02 for ANN. The results also establish efficient design with reduced power consumption of 3.52 W for 64-bit response generation when compared with existing state of the art PUF designs.